Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA

Authors

  • Ahmed Alhomoud Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Refka Ghodhbani Department of Computer Sciences, Faculty of Computing and information Technology, Northern Border University, Saudia Arabia | Electronics and Micro-Electronics Laboratory, Faculty of Sciences, Monastir University, Tunisia
  • Taoufik Saidani Department of Computer Sciences, Faculty of Computing and information Technology, Northern Border University, Saudi Arabia | Electronics and Micro-Electronics Laboratory, Faculty of Sciences, Monastir University, Tunisia
  • Hafedh Mahmoud Zayani Department of Electrical Engineering, College of Engineering, Northern Border University, Saudi Arabia
  • Yahia Said Department of Electrical Engineering, College of Engineering, Northern Border University, Saudi Arabia
  • Mohamed Ben Ammar Department of Information Systems, Faculty of Computing and Information Technology, Northern Border, Saudi Arabia
  • Jihane Ben Slimane Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
Volume: 14 | Issue: 2 | Pages: 13547-13553 | April 2024 | https://doi.org/10.48084/etasr.7081

Abstract

This paper presents a novel approach for fast FPGA prototyping of the Canny edge detection algorithm using High-Level Synthesis (HLS) based on the HDL Coder. Traditional RTL-based design methodologies for implementing image processing algorithms on FPGAs can be time-consuming and error-prone. HLS offers a higher level of abstraction, enabling designers to focus on algorithmic functionality while the tool automatically generates efficient hardware descriptions. This advantage was exploited by implementing the Canny edge detection algorithm in MATLAB/Simulink and utilizing the HDL Coder to automatically convert it into synthesizable VHDL code. This design flow significantly reduces development time and complexity compared to the traditional RTL approach. The experimental results showed that the HLS-based Canny edge detector achieved real-time performance on a Xilinx FPGA platform, showcasing the effectiveness of the proposed approach for fast FPGA prototyping in image processing applications.

Keywords:

FPGA, high-level synthesis, HDL coder, Canny edge detection, image processing, fast prototyping

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How to Cite

[1]
A. Alhomoud, “Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA”, Eng. Technol. Appl. Sci. Res., vol. 14, no. 2, pp. 13547–13553, Apr. 2024.

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