Hardware Acceleration for Object Detection using YOLOv5 Deep Learning Algorithm on Xilinx Zynq FPGA Platform

Authors

  • Taoufik Saidani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia | Laboratory of Electronics and Microelectronics (EμE), Faculty of Sciences, Monastir University, Tunisia
  • Refka Ghodhbani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia | Laboratory of Electronics and Microelectronics (EμE), Monastir University, Faculty of Sciences, Tunisia
  • Ahmed Alhomoud Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Ahmad Alshammari Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Hafedh Zayani Department of Electrical Engineering, Faculty of Engineering, Northern Border University, Saudi Arabia
  • Mohammed Ben Ammar Department of Information Systems, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
Volume: 14 | Issue: 1 | Pages: 13066-13071 | February 2024 | https://doi.org/10.48084/etasr.6761

Abstract

Object recognition presents considerable difficulties within the domain of computer vision. Field-Programmable Gate Arrays (FPGAs) offer a flexible hardware platform, having exceptional computing capabilities due to their adaptable topologies, enabling highly parallel, high-performance, and diverse operations that allow for customized reconfiguration of integrated circuits to enhance the effectiveness of object detection accelerators. However, there is a scarcity of assessments that offer a comprehensive analysis of FPGA-based object detection accelerators, and there is currently no comprehensive framework to enable object detection specifically tailored to the unique characteristics of FPGA technology. The You Only Look Once (YOLO) algorithm is an innovative method that combines speed and accuracy in object detection. This study implemented the YOLOv5 algorithm on a Xilinx® Zynq-7000 System on a Chip (SoC) to perform real-time object detection. Using the MS-COCO dataset, the proposed study showed an improvement in resource utilization with approximately 42 thousand (78%) look-up tables, 56 thousand (52%) flip-flops, 65 (46%) BRAMs, and 19 (9%) DSPs at a frequency of 250 MHz, improving the effectiveness compared to previous simulated results.

Keywords:

object detection, YOLOv5, high level synthesis, FPGA, HDL coder

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References

T. Saidani, "Deep Learning Approach: YOLOv5-based Custom Object Detection," Engineering, Technology & Applied Science Research, vol. 13, no. 6, pp. 12158–12163, Dec. 2023.

R. Ghodhbani, T. Saidani, A. Alhomoud, A. Alshammari, and R. Ahmed, "Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis," Engineering, Technology & Applied Science Research, vol. 13, no. 6, pp. 12169–12174, Dec. 2023.

R. Girshick, J. Donahue, T. Darrell, and J. Malik, "Rich Feature Hierarchies for Accurate Object Detection and Semantic Segmentation," in 2014 IEEE Conference on Computer Vision and Pattern Recognition, Columbus, OH, USA, Jun. 2014, pp. 580–587.

A. B. Amjoud and M. Amrouch, "Object Detection Using Deep Learning, CNNs and Vision Transformers: A Review," IEEE Access, vol. 11, pp. 35479–35516, 2023.

X. Yang, C. Zhuang, W. Feng, Z. Yang, and Q. Wang, "FPGA Implementation of a Deep Learning Acceleration Core Architecture for Image Target Detection," Applied Sciences, vol. 13, no. 7, Jan. 2023, Art. no. 4144.

A. Bochkovskiy, C. Y. Wang, and H. Y. M. Liao, "YOLOv4: Optimal Speed and Accuracy of Object Detection." arXiv, Apr. 22, 2020.

A. Boutros, S. Yazdanshenas, and V. Betz, "You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference," ACM Transactions on Reconfigurable Technology and Systems, vol. 11, no. 3, Sep. 2018.

R. Rajamohanan and B. C. Latha, "An Optimized YOLO v5 Model for Tomato Leaf Disease Classification with Field Dataset," Engineering, Technology & Applied Science Research, vol. 13, no. 6, pp. 12033–12038, Dec. 2023.

A. Shawahna, S. M. Sait, and A. El-Maleh, "FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review," IEEE Access, vol. 7, pp. 7823–7859, 2019.

E. Wang et al., "Deep Neural Network Approximation for Custom Hardware: Where We’ve Been, Where We’re Going," ACM Computing Surveys, vol. 52, no. 2, Feb. 2019.

M. A. Dias and D. A. P. Ferreira, "Deep Learning in Reconfigurable Hardware: A Survey," in 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Rio de Janeiro, Brazil, Feb. 2019, pp. 95–98.

Q. C. Mao, H. M. Sun, Y. B. Liu, and R.-S. Jia, "Mini-YOLOv3: Real-Time Object Detector for Embedded Applications," IEEE Access, vol. 7, pp. 133529–133538, 2019.

A. H. A. El-Shafie and S. E. D. Habib, "Survey on hardware implementations of visual object trackers," IET Image Processing, vol. 13, no. 6, pp. 863–876, 2019.

J. Wang, J. Lin, and Z. Wang, "Efficient Hardware Architectures for Deep Convolutional Neural Network," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 6, pp. 1941–1953, Jun. 2018.

C. Ding, S. Wang, N. Liu, K. Xu, Y. Wang, and Y. Liang, "REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs," in Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, Oct. 2019, pp. 33–42.

H. Nakahara, H. Yonekawa, T. Fujii, and S. Sato, "A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA," in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, Oct. 2018, pp. 31–40.

A. G. Blaiech, K. Ben Khalifa, C. Valderrama, M. A. C. Fernandes, and M. H. Bedoui, "A Survey and Taxonomy of FPGA-based Deep Learning Accelerators," Journal of Systems Architecture, vol. 98, pp. 331–345, Sep. 2019.

A. HajiRassouliha, A. J. Taberner, M. P. Nash, and P. M. F. Nielsen, "Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms," Signal Processing: Image Communication, vol. 68, pp. 101–119, Oct. 2018.

P. Babu and E. Parthasarathy, "Reconfigurable FPGA Architectures: A Survey and Applications," Journal of The Institution of Engineers (India): Series B, vol. 102, no. 1, pp. 143–156, Feb. 2021.

K. Tong, Y. Wu, and F. Zhou, "Recent advances in small object detection based on deep learning: A review," Image and Vision Computing, vol. 97, May 2020, Art. no. 103910.

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How to Cite

[1]
T. Saidani, R. Ghodhbani, A. Alhomoud, A. Alshammari, H. Zayani, and M. Ben Ammar, “Hardware Acceleration for Object Detection using YOLOv5 Deep Learning Algorithm on Xilinx Zynq FPGA Platform”, Eng. Technol. Appl. Sci. Res., vol. 14, no. 1, pp. 13066–13071, Feb. 2024.

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