An FPGA Accelerator for Real Time Hyperspectral Images Compression based on JPEG2000 Standard
Received: 1 January 2024 | Revised: 14 January 2024 | Accepted: 15 January 2024 | Online: 24 January 2024
Corresponding author: Refka Ghodhbani
Abstract
Lossless hyperspectral images have the advantage of reducing the data size, hence saving on storage and transmission costs. This study presents a dynamic pipeline hardware design for compressing and decompressing images using the Joint Photographic Experts Group-Lossless (JPEG2000) algorithm. The proposed architecture was specifically tailored for implementation on a Field Programmable Gate Array (FPGA) to accomplish efficient image processing. The introduction of a pipeline pause mechanism effectively resolves the issue of coding errors deriving from parameter modifications. Bit-plane coding was employed to enhance the efficacy of image coding calculations, leading to a reduction of parameter update delays. However, the context and decision creation procedure were streamlined, resulting in a significant enhancement in throughput. A hardware module utilizing the parallel block compression architecture was developed for JPEG2000 compression/decompression, allowing for configurable block size and bringing about enhanced image, compression/decompression, throughput, and reduced times. Verification results were obtained by implementing the proposed JPEG 2000 compression on a Zynq-7000 system-on-chip. The purpose of this system was to enable on-board satellite processing of hyperspectral image cubes with a specific focus on achieving lossless compression. The proposed architecture outperformed previous approaches by using fewer resources and achieving a higher compression ratio and clock frequency.
Keywords:
hyperspectral image compression, JPEG2000, EBCOT, MQ coder, FPGA, Zynq70000Downloads
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Copyright (c) 2024 Refka Ghodhbani, Layla Horrigue, Taoufik Saidani, Asaad M. Algarni, Muteb Alshammari
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