Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA
Received: 16 February 2024 | Revised: 24 February 2024 and 25 February 2024 | Accepted: 27 February 2024 | Online: 3 March 2024
Corresponding author: Taoufik Saidani
Abstract
This paper presents a novel approach for fast FPGA prototyping of the Canny edge detection algorithm using High-Level Synthesis (HLS) based on the HDL Coder. Traditional RTL-based design methodologies for implementing image processing algorithms on FPGAs can be time-consuming and error-prone. HLS offers a higher level of abstraction, enabling designers to focus on algorithmic functionality while the tool automatically generates efficient hardware descriptions. This advantage was exploited by implementing the Canny edge detection algorithm in MATLAB/Simulink and utilizing the HDL Coder to automatically convert it into synthesizable VHDL code. This design flow significantly reduces development time and complexity compared to the traditional RTL approach. The experimental results showed that the HLS-based Canny edge detector achieved real-time performance on a Xilinx FPGA platform, showcasing the effectiveness of the proposed approach for fast FPGA prototyping in image processing applications.
Keywords:
FPGA, high-level synthesis, HDL coder, Canny edge detection, image processing, fast prototypingDownloads
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Copyright (c) 2024 Ahmed Alhomoud , Refka Ghodhbani, Taoufik Saidani, Hafedh Zayani, Yahia Said, Mohamed Ben Ammar, Jehan Ben Slimane
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