Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis

Authors

  • Refka Ghodhbani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Rafha, Saudi Arabia | Laboratory of Electronics and Microelectronics (EμE), Faculty of Sciences, Monastir University, Tunisia
  • Taoufik Saidani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Rafha, Saudi Arabia | Laboratory of Electronics and Microelectronics (EμE), Faculty of Sciences, Monastir University, Tunisia
  • Ahmed Alhomoud Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Rafha, Saudi Arabia
  • Ahmad Alshammari Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Rafha, Saudi Arabia
  • Rabie Ahmed Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Rafha, Saudi Arabia | Department of Mathematics and Computer Science, Faculty of Science, Beni-Suef University, Egypt
Volume: 13 | Issue: 6 | Pages: 12169-12174 | December 2023 | https://doi.org/10.48084/etasr.6406

Abstract

Computer vision systems use corner detection to identify features in an image. In applications such as motion detection, tracking, picture registration, and object recognition, corner detection is often one of the initial steps. In this paper, a real-time image processing system based on Harris corner detection was designed and implemented using Zynq architecture and model-based design tools. The system was based on a development board containing the Zynq-7000 chip, which consists of a combination of FPGA and microprocessor, and the image taken with a high-resolution camera was processed in real-time by applying color conversion and Harris corner detection. The filter hardware designs used in the system were made using the HDL Coder tool in Matlab/Simulink without writing HDL code. The hardware that receives images from the camera was designed on a model-based basis with the Xilinx Vivado 2020. The HDL code that was implemented on the Xilinx ZedBoard using Vivado software was then validated to ensure real-time operation with the incoming video stream. The results achieved exhibited superiority compared to prior implementations in terms of area efficiency (reduced number of gates on the target FPGA) and speed performance on an identical target card. Using the rapid prototyping approach, two alternative hardware accelerator designs were created using various high-level synthesis tools. This design used less than 50% of the host FPGA's logic resources and was at least 30% faster than current implementations.

Keywords:

rapid prototyping, automated hardware design, corner detection codesign, MBD, HDL coder, Xilinx Zynq-7000

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References

V. H. Schulz, F. G. Bombardelli, and E. Todt, "A Harris Corner Detector Implementation in SoC-FPGA for Visual SLAM," in Robotics, Uberlândia, Brazil, 2016, pp. 57–71. DOI: https://doi.org/10.1007/978-3-319-47247-8_4

C. Cabani, "Implementation of an affine-invariant feature detector in field-programmable gate arrays," MSc Thesis, University of Toronto, Toronto, Canada, 2006.

T. Saidani and R. Ghodhbani, "Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform," Engineering, Technology & Applied Science Research, vol. 12, no. 1, pp. 8007–8012, Feb. 2022. DOI: https://doi.org/10.48084/etasr.4615

S. Liu et al., "Real-time implementation of harris corner detection system based on FPGA," in 2017 IEEE International Conference on Real-time Computing and Robotics (RCAR), Okinawa, Japan, Jul. 2017, pp. 339–343. DOI: https://doi.org/10.1109/RCAR.2017.8311884

C. Xu and Y. Bai, "Implementation Of Harris Corner Matching Based On FPGA," presented at the 2017 6th International Conference on Energy and Environmental Protection (ICEEP 2017), Jun. 2017, pp. 807–811. DOI: https://doi.org/10.2991/iceep-17.2017.141

T. L. Chao and K. H. Wong, "An efficient FPGA implementation of the Harris corner feature detector," in 2015 14th IAPR International Conference on Machine Vision Applications (MVA), Tokyo, Japan, Feb. 2015, pp. 89–93. DOI: https://doi.org/10.1109/MVA.2015.7153140

C. Y. Lee, H. J. Wang, C. M. Chen, C. C. Chuang, Y. C. Chang, and N. S. Chou, "A Modified Harris Corner Detection for Breast IR Image," Mathematical Problems in Engineering, vol. 2014, Jul. 2014, Art. no. e902659. DOI: https://doi.org/10.1155/2014/902659

H. Mestiri, I. Barraj, and M. Machhout, "AES High-Level SystemC Modeling using Aspect Oriented Programming Approach," Engineering, Technology & Applied Science Research, vol. 11, no. 1, pp. 6719–6723, Feb. 2021. DOI: https://doi.org/10.48084/etasr.3971

S. S. Rafiammal, D. N. Jamal, and S. K. Mohideen, "Reconfigurable Hardware Design for Automatic Epilepsy Seizure Detection using EEG Signals," Engineering, Technology & Applied Science Research, vol. 10, no. 3, pp. 5803–5807, Jun. 2020. DOI: https://doi.org/10.48084/etasr.3419

"Vivado Design Suite User Guide: High-Level Synthesis," Xilinx, UG902 (v2018.3), 2018.

"Mathworks HDL Coder." https://www.mathworks.com/products/hdl-coder.html.

J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang, "High-Level Synthesis for FPGAs: From Prototyping to Deployment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, pp. 473–491, Apr. 2011. DOI: https://doi.org/10.1109/TCAD.2011.2110592

R. A. Bergamaschi et al., "High-level synthesis in an industrial environment," IBM Journal of Research and Development, vol. 39, no. 1.2, pp. 131–148, Jan. 1995. DOI: https://doi.org/10.1147/rd.391.0131

K. Kucukcakar, C. T. Chen, J. Gong, W. Philipsen, and T. E. Tkacik, "Matisse: an architectural design tool for commodity ICs," IEEE Design & Test of Computers, vol. 15, no. 2, pp. 22–33, Apr. 1998. DOI: https://doi.org/10.1109/54.679205

P. E. R. Lippens et al., "PHIDEO: a silicon compiler for high speed algorithms," in Proceedings of the European Conference on Design Automation, Amsterdam, Netherlands, Oct. 1991, pp. 436–441.

J. Biesenack et al., "The Siemens high-level synthesis system CALLAS," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 3, pp. 244–253, Sep. 1993. DOI: https://doi.org/10.1109/92.238438

D. W. Knapp, Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler. Englewood Cliffs, NJ, USA: Prentice Hall PTR, 1996.

"Catapult High-Level Synthesis & Verification | Siemens Software." https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/.

"Stratus High-Level Synthesis." https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html.

"Mathworks HDL Verifier." https://www.mathworks.com/products/hdl-verifier.html.

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How to Cite

[1]
R. Ghodhbani, T. Saidani, A. Alhomoud, A. Alshammari, and R. Ahmed, “Real Time FPGA Implementation of an Efficient High Speed Harris Corner Detection Algorithm Based on High-Level Synthesis”, Eng. Technol. Appl. Sci. Res., vol. 13, no. 6, pp. 12169–12174, Dec. 2023.

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