Efficient Hardware Accelerator and Implementation of JPEG 2000 MQ Decoder Architecture

Authors

  • Layla Horrigue Electronics and Micro-Electronics Laboratory, Faculty of Sciences, Monastir University, Tunisia
  • Refka Ghodhbani Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Albia Maqbool Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Eman H. Abd-Elkawy Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia | Department of Mathematics and Computer Science, Faculty of Science, Beni-Suef University, Egypt
  • Jihane Ben Slimane Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Taoufik Saidani Department of Computer Sciences, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Faheed A. F. Alrslani Department of Information Technology, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Amjad A. Alsuwaylimi Department of Information Technology, College of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Marouan Kouki Department of Information Systems, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
  • Amani Kachoukh Department of Information Systems Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia
Volume: 14 | Issue: 2 | Pages: 13463-13469 | April 2024 | https://doi.org/10.48084/etasr.7065

Received: 13 February 2024 | Revised: 23 February 2024 | Accepted: 24 February 2024 | Online: 29 February 2024


Corresponding author: Refka Ghodhbani

Abstract

Due to the extensive use of multimedia technologies, there is a pressing need for advancements and enhanced efficiency in picture compression. JPEG 2000 standard aims to meet the needs for encoding still pictures. JPEG 2000 is an internationally recognized standard for compressing still images. It provides a wide range of features and offers superior compression ratios and interesting possibilities when compared to traditional JPEG approaches. Nevertheless, the MQ decoder in the JPEG 2000 standard presents a substantial obstacle for real-time applications. In order to fulfill the demands of real-time processing, it is imperative to meticulously devise a high-speed MQ decoder architecture. This work presents a novel MQ decoder architecture that is both high-speed and area-efficient, making it comparable to previous designs and well-suited for chip implementation. The design is implemented using the VHDL hardware description language and is synthesized with Xilinx ISE 14.7 and Vivado 2015.1. The implementation findings show that the design functions at a frequency of 438.5 MHz on Virtex-6 and 757.5 MHz on Zync7000. For these particular frequencies, the calculated frame rate is 63.1 frames per second.

Keywords:

JPEG2000, MQ decoder, FPGA, EBCOT, implementation

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References

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How to Cite

[1]
L. Horrigue, “Efficient Hardware Accelerator and Implementation of JPEG 2000 MQ Decoder Architecture”, Eng. Technol. Appl. Sci. Res., vol. 14, no. 2, pp. 13463–13469, Apr. 2024.

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Copyright (c) 2024 Layla Horrigue, Refka Ghodhbani, Albia Maqbool, Emane H. Abd. Elkawy, Jihane Ben Slimane, Taoufik Saidani, Faheed A. F. Alrslani, Amjad A. Alsuwaylimi, Marouan Kouki, Amani Kachoukh

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