Design of a Low Power CMOS Inverter with the VBB Stack Approach


  • S. Khmailia Department of Physics, Faculty of Science, University of Tunis El Manar, Tunisia
  • J. Rouabeh Department of Physics, Faculty of Science, University of Tunis El Manar, Tunisia
  • A. Mami Laboratory of Application of Energy, Efficiency and Renewable Energies, Tunis El Manar University, Tunisia
Volume: 12 | Issue: 4 | Pages: 8891-8895 | August 2022 |


Due to the exponential advancement in nanotechnology devices, low energy consumption has become a significant concern of researchers and VLSI designers. In this paper, the Variable body bias (VBB) and the stack approach are used simultaneously to reduce the leakage power of a CMOS inverter in standby mode. This new technique is called the VBB stack approach. The simulations have been conducted on the LT spice simulator. The power evaluation has been determined and compared between the conventional approach, the stack approach, and the VBB stack approach. The results have demonstrated the performance of the VBB stack approach. The power consumption in the VBB stack approach has decreased by 23% compared to the conventional approach and by 10% compared to the stack approach.


CMOS inverter, VLSI, power dissipation, leakage current, low power, VBB stack approach


Download data is not yet available.


H. Ghabri, D. B. Issa, and H. Samet, "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor," Engineering, Technology & Applied Science Research, vol. 9, no. 6, pp. 4933–4936, Dec. 2019. DOI:

M. Ma, Z. Li, and Z. Yao, "Current-mode CMOS Active Inductor with Applications to Low-Voltage Oscillators," Engineering, Technology & Applied Science Research, vol. 3, no. 6, pp. 540–543, Dec. 2013. DOI:

W. W. Kai, N. binti Ahmad, and M. H. bin Jabbar, "Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power," International Journal of Electrical and Computer Engineering, vol. 7, no. 6, pp. 3010–3019, Dec. 2017. DOI:

B. L. Dokic, "A Review on Energy Efficient CMOS Digital Logic," Engineering, Technology & Applied Science Research, vol. 3, no. 6, pp. 552–561, Dec. 2013. DOI:

M. J. Rani and S. Malarkkan, "Analysis of Pseudo-NMOS Logic with Reduced Static Power in Deep Sub- Micron Regime," International Journal of Advances in Electronics Engineering, vol. 2, no. 3, pp. 233–236, Dec. 2012.

A. A. Beltran Jr, K. Nones, R. L. Salanguit, J. B. Santos, J. M. R. Santos, and K. J. Dizon, "Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique," Journal of Robotics and Control, vol. 2, no. 4, pp. 252–257, Jul. 2021. DOI:

H. Pasha, "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique at 90nm Technology," vol. 4, no. 8, pp. 43–48, Aug. 2016.

P. Kalyani, M. M. Latha, and P. C. Sekhar, "Analysis of MOS transistor behavior with Forward and Reverse Body biasing in Subthreshold region," vol. 13, no. 19, pp. 14236–14240, 2018.

J. W. Chun and C.-Y. R. Chen, "Leakage power reduction using the body bias and pin reordering technique," IEICE Electronics Express, vol. 13, no. 3, 2016, Art. no. 13.20151052. DOI:

M. Zabeli, "The most significant MOSFET parameters impact in CMOS inverter switching characteristics," International Journal Of Circuits, Systems And Signal Processing, vol. 12, pp. 565–572, May 2018.

L. Kumre, B. P. Shrivastava, and N. Rai, "Comparative Analysis Of Cmos Inverter For Low Leakage Power," International Journal Of Scientific & Technology Research, vol. 8, no. 9, pp. 1598–1601, Sep. 2019.

M. V. Ramanaiah, S. Alluri, B. R. Naik, and N. S. S. Reddy, "Transistor sizing of CMOS VLSI Circuits in Deep Submicron Technology," International Journal of Innovative Technology and Exploring Engineering, vol. 8, no. 11S2, pp. 15–29, Oct. 2019. DOI:

M. Gangele and K. P. Patra, "Comparative Analysis of Lector and Stack Technique to Reduce the Leakage Current in CMOS Circuits," International Journal of Research in Engineering and Technology, vol. 4, no. 7, pp. 92–100, Jul. 2015. DOI:

S. Nehra and P. K. Ghosh, "Design of a Low Power XNOR gate Using MTCMOS Technique," Advance in Electronic and Electric Engineering, vol. 3, no. 6, pp. 701–710, 2013.

N. Hanchate and N. Ranganathan, "LECTOR: a technique for leakage reduction in CMOS circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 196–205, Oct. 2004. DOI:

S. I. Padma, M. Shamila, P. Rahima, and M. A. Devi, "Leakage Power Reduction Techniques for Nanoscale in CMOS VLSI Systems Using Microwind Eda Tool," International Research Journal of Engineering and Technology, vol. 7, no. 5, pp. 2835–2840, May 2020.


How to Cite

S. Khmailia, J. Rouabeh, and A. Mami, “Design of a Low Power CMOS Inverter with the VBB Stack Approach”, Eng. Technol. Appl. Sci. Res., vol. 12, no. 4, pp. 8891–8895, Aug. 2022.


Abstract Views: 234
PDF Downloads: 133

Metrics Information
Bookmark and Share

Most read articles by the same author(s)