A Hardware-Accelerated Analytical Framework for Dynamic Physical Layer Selection in Hybrid Low-Power Wide-Area Network Systems

Wendyam Clovis Dubois Zongo; Nicasio Maguu Muchuka; Irene Muisyo

doi:10.48084/etasr.18926

Authors

Wendyam Clovis Dubois Zongo Department of Electrical Engineering, Pan African University Institute for Basic Sciences, Technology and Innovation, hosted at Jomo Kenyatta University of Agriculture and Technology, Nairobi, Kenya
Nicasio Maguu Muchuka Department of Electrical and Control Engineering, Faculty of Engineering and Technology, Egerton University, Nakuru, Kenya
Irene Muisyo Department of Electronic and Computer Engineering, Jomo Kenyatta University of Agriculture and Technology, Nairobi, Kenya

Volume: 16 | Issue: 4 | Pages: 37610-37619 | August 2026 | https://doi.org/10.48084/etasr.18926

Received: 25 March 2026 | Revised: 11 May 2026 | Accepted: 27 May 2026 | Online: 13 June 2026

Corresponding author: Wendyam Clovis Dubois Zongo

Abstract

Low-Power Wide-Area Networks (LPWANs) are a key technology for Internet of Things (IoT) applications due to their energy efficiency and long-range capability. However, system performance strongly depends on selecting appropriate physical layer (PHY) configurations under varying channel and traffic conditions. This paper proposes an analytical framework for dynamic PHY selection in hybrid LPWAN systems integrating Long Range (LoRa) and Orthogonal Frequency Division Multiplexing (OFDM) technologies. The framework derives closed-form expressions for packet airtime, energy consumption per bit, end-to-end latency, and effective throughput for both PHY technologies and combines them into a normalized multi-objective cost function. A feasibility filtering step ensures that only PHY configurations satisfying minimum Signal-to-Noise Ratio (SNR) requirements are considered, preventing incorrect selections under marginal channel conditions. The framework is implemented as a hardware-accelerated decision engine on a Xilinx Zynq-7000 Field-Programmable Gate Array (FPGA), requiring 1,105 Look-Up Tables (LUTs) and 1,227 flip-flops, demonstrating computational feasibility without requiring RF-level validation. Evaluation across seven SNR levels (−5 to 12 dB) and three payload sizes (45 to 500 bytes) shows that LoRa SF7 is selected at low SNR, achieving 92.42 ms latency and 6.45 µJ/bit energy at 45 bytes, whereas OFDM 16-QAM 1/2 is selected at high SNR, achieving 1.38 ms latency and 0.097 µJ/bit energy consumption. The proposed framework achieves up to 67 times lower latency and 66 times lower energy consumption compared to LoRa under favorable channel conditions.

Keywords:

LPWAN, dynamic PHY selection, LoRa–OFDM hybrid communication, FPGA-based accelerator, Internet of Things (IoT)

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