A CIM-Based Implementation of 7-Segment Decoder Using Low-Leakage 8T SRAM Cells

P. Deepika; N. Shylashree

doi:10.48084/etasr.15105

Authors

P. Deepika Department of ECE, RV College of Engineering, Bangalore, India | Visvesvaraya Technological University, Belagavi, Karnataka, India https://orcid.org/0000-0003-2009-5935
N. Shylashree Department of ECE, RV College of Engineering, Bangalore, India | Visvesvaraya Technological University, Belagavi, Karnataka, India

Volume: 16 | Issue: 3 | Pages: 35334-35340 | June 2026 | https://doi.org/10.48084/etasr.15105

Received: 25 September 2025 | Revised: 25 October 2025, 9 December 2025, 30 January 2026, and 5 March 2026 | Accepted: 17 March 2026 | Online: 28 April 2026

Corresponding author: N. Shylashree

Abstract

Computation-in-Memory (CIM) is an emerging paradigm that aims to overcome the performance and energy bottlenecks of traditional von Neumann architectures. In conventional systems, data are constantly shuttled back and forth between the memory unit and the processing unit, resulting in significant latency, high energy consumption, and bandwidth limitation, often referred to as the memory wall problem. CIM commonly employs 8T Static Random-Access Memory (SRAM) cells, as their decoupled read and write ports allow reliable in-memory operations. Compared to conventional 6T SRAM, the 8T design provides improved stability and better support for parallel computation. This makes 8T SRAM a strong candidate for energy-efficient and high-performance CIM architectures. However, the sleep-based pass transistor for read operation faces limitations, as the absence of a dedicated data retention mechanism results in potential data loss. The proposed design uniquely integrates CIM with a low-leakage 8T SRAM cell to enable direct logic implementation within memory, significantly reducing power and latency. This paper implements a CIM-based seven-segment decoder using a low-power data retention 8T SRAM cell, which demonstrates a 51% reduction in processing delay and a 56% decrease in power consumption during read/write operations. The complete decoder circuit has a power consumption of 36.89 µW and occupies an area of 1.509 mm², as confirmed through Cadence Virtuoso environment simulation utilizing gpdk45 technology.

Keywords:

8T SRAM, Computation-in-Memory (CIM), decoder design, low-leakage SRAM, memory design

Downloads

Download data is not yet available.

References

M. A. Turi and J. G. Delgado-Frias, "Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 765–769, Apr. 2020.

A. K. Rajput and M. Pattanaik, "Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation," in 2020 International Conference for Emerging Technology, Belgaum, India, 2020, pp. 1–5.

J. Han and Y. Kim, "A Fast Half Adder using 8T SRAM for Computation-in-Memory," in 2021 IEEE International Conference on Consumer Electronics-Asia, Gangwon, Republic of Korea, 2021, pp. 1–3.

D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proceedings of the IEEE, vol. 89, no. 3, pp. 259–288, Mar. 2001.

D. Prabhakar, N. Shylashree, S. Y. Narasimhaiah, Y. B. Mariswamappa, and S. S. Hemaraj, "A fast half-subtractor using 8T static random access memory for in-memory computation," International Journal of Reconfigurable and Embedded Systems, vol. 14, no. 1, pp. 273–281, Mar. 2025.

B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, July 2004.

A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy, "8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2556–2567, Nov. 2019.

S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, "Computing in Memory With Spin-Transfer Torque Magnetic RAM," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470–483, Mar. 2018.

A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, "X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219–4232, Dec. 2018.

N. Verma et al., "In-Memory Computing: Advances and Prospects," IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 43–55, 2019.

J. Mu and B. Kim, "A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks," in 2020 IEEE International Symposium on Circuits and Systems, Seville, Spain, 2020, pp. 1–4.

P. P. Ravichandiran and P. D. Franzon, "A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation," in 2021 IEEE International 3D Systems Integration Conference, Raleigh, NC, USA, 2021, pp. 1–6.

G. Manikannan, K. Mahendran, and P. Prabakaran, "Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates in 90nm Technology," in 2017 International Conference on Technical Advancements in Computers and Communications, Melmaurvathur, India, 2017, pp. 61–65.

A. Bhaskar, "Design and analysis of low power SRAM cells," in 2017 Innovations in Power and Advanced Computing Technologies, Vellore, India, 2017, pp. 1–5.

A. Manna and V. S. K. Bhaaskaran, "Improved read noise margin characteristics for single bit line SRAM cell using adiabatically operated word line," in 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software, Chennai, India, 2017, pp. 385–393.

L. Ammoura, M. L. Flottes, P. Girard, and A. Virazel, "Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures," in 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Montpellier, France, 2021, pp. 1–4.

W. Choi, J. Park, and G. Kang, "Dynamic stability estimation for latch-type voltage sense amplifier," in 2014 International SoC Design Conference, Jeju, South Korea, 2014, pp. 218–219.

S. Fairooz, P. Thanapal, P. Ganesan, M. S. Prakash Balaji, and V. Elamaran, "Revisiting the Utility of Transmission Gate and Passtransistor Logic Styles in CMOS VLSI Design," in 2021 3rd International Conference on Signal Processing and Communication, Coimbatore, India, 2021, pp. 276–280.

M. Kutila, A. Paasio, and T. Lehtonen, "Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation," in 2014 IEEE 57th International Midwest Symposium on Circuits and Systems, College Station, TX, USA, 2014, pp. 925–928.

D. B. L. Quoc, P. L. Vo, P. N. P. Thien, and L. Tran, "High-Performance In-Memory XNOR Computing: A 65 nm 12T SRAM Architecture for Neural Network Acceleration," Engineering, Technology & Applied Science Research, vol. 15, no. 4, pp. 24930–24939, Aug. 2025.

P. Athe and S. Dasgupta, "A comparative study of 6T, 8T and 9T decanano SRAM cell," in 2009 IEEE Symposium on Industrial Electronics & Applications, Kuala Lumpur, Malaysia, 2009, pp. 889–894.

D. Mittal and V. K. Tomar, "Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node," in 2020 11th International Conference on Computing, Communication and Networking Technologies, Kharagpur, India, 2020, pp. 1–4.

Y. Liu et al., "A Compact Model for Relaxation Effect in Analog RRAM for Computation-in-Memory System Design and Benchmark," in 2021 5th IEEE Electron Devices Technology & Manufacturing Conference, Chengdu, China, 2021, pp. 1–3.

A. Chandras and V. S. K. Bhaaskaran, "Sensing schemes of sense amplifier for single-ended SRAM," in 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software, Chennai, India, 2017, pp. 379–384.

H. Jeong et al., "Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 6, pp. 1555–1563, 2015.

V. N. R and S. Hiremath, "Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level," International Journal of Engineering Research & Technology, vol. 11, no. 7, pp. 310–314, July 2022.