SRAM Design and Analysis Using TIGFET
Corresponding author: S. Nagaleela
Abstract
Continuous CMOS scaling can be enabled with nanowire transistor technologies such as the Three Independent Gate FET (TIGFET). TIGFET can further reduce the leakage current compared to FinFET, using Schottky barriers, increasing the speed of operation. As technology nodes become smaller, the number of Static Random Access Memory (SRAM) cells connected to a single word line grows, leading to an increase in coupling capacitance. With this, the power consumption of the SRAM increases, and the performance is degraded. A fundamental 6-T SRAM cell was developed utilizing TIGFET on a 10nm scale, and its performance was evaluated based on stability, leakage power, average power, and delay metrics. Write delays of 40 ns and read delays of 38.7 ns show better performance compared to a MOSFET-based design. The SNM values for TIGFET-SRAM were 0.36 V, 0.25 V, and 0.32 V in hold, write, and read modes, respectively, offering good stability. The design was simulated using the Synopsys HSPICE tool, and its results were compared with those of a MOSFET-SRAM cell.
Keywords:
TIGFET, SRAM, high-performance, leakage power, static-noise-margin, reconfigurable devicesDownloads
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