Design and Performance Analysis of Power-Efficient Multipliers for Image Sharpening

Tanya Mendez; Manjunatha Badiger

doi:10.48084/etasr.13232

Authors

Tanya Mendez Nitte (Deemed to be University), NMAM Institute of Technology (NMAMIT), Nitte, Department of Robotics and Artificial Intelligence, Udupi, India
Manjunatha Badiger Nitte (Deemed to be university), NMAM Institute of Technology (NMAMIT), Nitte, Department of VLSI Design and Technology, Udupi, India https://orcid.org/0000-0001-8073-0270

Volume: 15 | Issue: 6 | Pages: 28460-28465 | December 2025 | https://doi.org/10.48084/etasr.13232

Received: 8 July 2025 | Revised: 24 July 2025, 6 August 2025, and 17 August 2025 | Accepted: 22 August 2025 | Online: 4 December 2025

Corresponding author: Tanya Mendez

Abstract

Strong motivation to reduce power consumption in portable devices with battery operation has driven research into novel power-efficient digital circuit approaches. Modern processors integrate complex multipliers, but increased computational complexity leads to longer delays and higher power consumption. The need for high-speed multipliers with low power consumption arises to achieve optimal performance of digital image and signal processing applications. The advent of emerging technologies is the driving force behind the design of multipliers with minimized power consumption, reduced delays, and smaller dimensions. This study presents a comparative analysis of various multiplier architectures and proposes two novel designs: (i) Low-Power Approximate Multiplier using the Nikhilam algorithm (LPAMN) and (ii) Efficient Carry-Save Multiplier with SBETA Optimization (ECSM-SBETA-O). These architectures leverage approximate computing techniques to minimize power consumption while maintaining computational accuracy. The proposed designs were implemented using the Cadence Genus tool with the GPDK-90 nm and GPDK-45 nm technology libraries. LPAMN achieved a significant 31.59% power reduction, along with 40.03% and 47.43% improvements in PDP and EDP, respectively, compared to existing designs. Furthermore, it enhanced image sharpening performance, achieving an improved PSNR of 32.16 dB. These results highlight the potential of the proposed designs for energy-efficient digital processing applications.

Keywords:

low-power, multiplier, Verilog, approximate computing, Vedic arithmetic, image processing

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