Optimal IIR Filter Design and FPGA Realization
Received: 20 June 2025 | Revised: 16 August 2025, 19 October 2025, and 2 November 2025 | Accepted: 3 November 2025 | Online: 30 November 2025
Corresponding author: Arunjyothi Eddla
Abstract
An Infinite Impulse Response (IIR) filter implemented on a Field-Programmable Gate Array (FPGA) provides low-area, high-speed Digital Signal Processing (DSP) with efficient hardware utilization. However, designing an IIR filter on an FPGA can be challenging due to the recursive nature of filters in fixed-point arithmetic processes, which makes it difficult to obtain numerical stability and minimize hardware resource usage. This research proposes the Array Multiplier-Optimal Adder-IIR (AM-OA-IIR) and Array Multiplier-Kogge-Stone Adder-IIR (AM-KSA-IIR) architectures to minimize hardware usage. The Carry Lookahead Adder (CLA) and the Carry Skip Adder (CSA) are combinations of the Optimal Adder (OA), which effectively manage multi-operand addition by minimizing carry propagation delay. The CSA performs rapid intermediate additions without immediate carry computation, whereas the CLA quickly resolves final carries. This integration reduces logic depth and minimizes the overall area required for the FPGA implementation. Furthermore, the KSA offers high-speed arithmetic by minimizing the delay caused by carry propagation through parallel computation. Therefore, the proposed AM-OA-IIR and AM-KSA-IIR achieve a logic element count of 379 and 486, respectively, for the Virtex5 FPGA device at order 8, compared to the logic element count of 1,024 for a conventional FIR-based IIR design.
Keywords:
Array Multiplier (AM), Carry Skip Adder (CSA), Infinite Impulse Response (IIR), Optimal Adder (OA)Downloads
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