High-Performance In-Memory XNOR Computing: A 65 nm 12T SRAM Architecture for Neural Network Acceleration
Received: 23 April 2025 | Revised: 13 May 2025 | Accepted: 1 June 2025 | Online: 13 June 2025
Corresponding author: Linh Tran
Abstract
This paper presents a 64×16 XNOR-SRAM array in 65nm CMOS technology for In-Memory Computing (IMC), designed to accelerate deep neural networks with low latency and high-power efficiency. Using a 12-transistor bitcell, the architecture performs XNOR-and-Accumulate (XAC) operations within the SRAM, reducing data movement. Cadence Spectre simulations show a 342.67 ps delay and 901.133 µW power consumption at 1.2 V, with robust ternary and binary operation. A flash Analog-to-Digital Converter (ADC) and an analog multiplexer enhance precision, despite minor nonlinearities from transistor mismatches. Compared to prior designs, the proposed XNOR-SRAM offers competitive latency for edge AI applications.
Keywords:
In-Memory Computing (IMC), SRAM, Deep Neural Network (DNN), low latency, power efficiencyDownloads
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Copyright (c) 2025 Doanh Bui Le Quoc, Phuoc Luan Vo, Phuc Nguyen Phan Thien, Linh Tran
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