A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design
Received: 5 December 2024 | Revised: 9 January 2025 | Accepted: 11 January 2025 | Online: 4 February 2025
Corresponding author: M. G. Anuradha
Abstract
Fast adders are utilized to cater for computationally intensive operations, and until recently, researchers have focused on optimizing the logic used in carry propagation. In the present study, a new methodology of implementation deploying the left-to-right Vedic addition method is proposed. The proposed methodology and the developed architecture add the number from the Most Significant Bit (MSB), where the carry generation is minimal, and reduce the complexity involved in the binary addition to optimize the area delay and power delay of the binary adder. The proposed left-to-right adder has been implemented for bit sizes of 8, 16, and 32. The synthesis results show that it outperforms existing adder techniques in terms of power-delay and area-delay products. The results indicate that the 32-bit left-to-right adder achieves an average reduction of 8% in the power-delay product and 23% in the area-delay product compared to current fast adders.
Keywords:
fast adders, VLSI, left-to-right adder, Vedic mathematics, VerilogDownloads
References
V. Vijay et al., "A Review On N-Bit Ripple-Carry Adder, Carry-Select Adder And Carry-Skip Adder," Journal of VLSI Circuits and Systems, vol. 4, no. 1, pp. 27–32, Jun. 2022.
V. Pudi and K. Sridharan, "Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA," IEEE Transactions on Nanotechnology, vol. 11, no. 1, pp. 105–119, Jan. 2012.
A. S. Hameed and M. J. Kathem, "High speed modified carry save adder using a structure of multiplexers," International Journal of Electrical and Computer Engineering (IJECE), vol. 11, no. 2, pp. 1591–1598, Apr. 2021.
M. S. Hossain and F. Arifin, "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder," AIUB Journal of Science and Engineering (AJSE), vol. 20, no. 2, pp. 1–7, May 2021.
K. Chirca et al., "A static low-power, high-performance 32-bit carry skip adder," in Euromicro Symposium on Digital System Design, 2004. DSD 2004, Rennes, France, 2004, pp. 615–619.
F. K. Gurkayna, Y. Leblebicit, L. Chaouati, and P. J. McGuinness, "Higher radix Kogge-Stone parallel prefix adder architectures," in 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, 2000, pp. 609–612 vol.5.
J. Lee, H. Seo, H. Seok, and Y. Kim, "A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation," IEEE Access, vol. 9, pp. 119939–119953, 2021.
D. S. Manikanta, K. S. S. Ramakrishna, M. Giridhar, N. Avinash, T. Srujan, and R. S. R, "Hardware Realization of Low power and Area Efficient Vedic MAC in DSP Filters," in 2021 5th International Conference on Trends in Electronics and Informatics, Tirunelveli, India, 2021, pp. 46–50.
N. Poornima and V. S. K. Bhaaskaran, "Design and Implementation of 32-Bit High Valency Jackson Adders," Journal of Circuits, Systems and Computers, vol. 26, no. 07, Jul. 2017, Art. no. 1750123.
H. T. Vergos and G. Dimitrakopoulos, "On Modulo 2^n+1 Adder Design," IEEE Transactions on Computers, vol. 61, no. 2, pp. 173–186, Feb. 2012.
S. K. Singhal, B. K. Mohanty, S. K. Patel, and G. Saxena, "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder," Journal of Circuits, Systems and Computers, vol. 29, no. 12, Sep. 2020, Art. no. 2050186.
J. M R and Manjudevi, "Analysis of Special Adders for Digital System," in 2021 5th International Conference on Trends in Electronics and Informatics, Tirunelveli, India, 2021, pp. 253–256.
A. K. Panda, R. Palisetty, and K. C. Ray, "High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3944–3953, Nov. 2020.
P. Jayakrishna, P. Sravani, R. S. Reddy, and S. Ashritha, "Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder," International Journal for Research in Applied Science and Engineering Technology, vol. 11, no. VI, pp. 1353–1361, Jun. 2023.
K. Deepthi, P. Bhaskar, M. Priyanka, B. V. Sonika, and B. N. Shashikala, "Design and Implementation of High-Speed Low-Power Carry Select Adder," in Cognitive Informatics and Soft Computing: Proceeding of CISC 2020, Balasore, Odisha, India, 2020, pp. 517–530.
Y.-Y. Chu, S.-H. Shieh, H. Feng, H. Deng, M.-S. Shiau, and D.-C. Huang, "A High-Speed Carry-Select Adder with Optimized Block Sizes," in 2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification, Xiamen, China, 2021, pp. 182–186.
P. Kavipriya, S. Lakshmi, T. Vino, M. R. Ebenezar Jebarani, and G. Jegan, "Booth Multiplier Design Using Modified Square Root Carry-Select-Adder," in 2021 International Conference on Artificial Intelligence and Smart Systems, Coimbatore, India, 2021, pp. 1647–1653.
O. Anjaneyulu and C. V. K. Reddy, "A novel design of full adder cell for VLSI applications," International Journal of Electronics, vol. 110, no. 4, pp. 670–685, Apr. 2023.
V. Vijay, J. Prathiba, S. N. Reddy, and V. R. Rao, "Energy efficient CMOS Full-Adder Designed with TSMC 0.18 μm Technology," in International Conference on Technology and Management, Hyderabad, India, 2011, pp. 356–361.
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