Direct ADC Controlled Asymmetric Cascaded Multilevel Inverter
Received: 28 June 2022 | Revised: 8 July 2022 | Accepted: 8 July 2022 | Online: 17 July 2022
Corresponding author: M. J. Shah
Abstract
This paper presents an asymmetric multi-level inverter with a novel direct ADC control scheme. This scheme does not use a carrier wave or a reference sinusoidal wave to generate gate pulses for power switches, but an Analog to Digital Converter (ADC) to create gate pulses. For n sources, n bit ADC will generate 2n+1-1 levels at the output voltage of the inverter. This scheme uses the ADC output for the gate pulses for power switching devices. In this topology, the inverter comprises a series of connected half-bridges to generate a more significant level. The presented topology uses binary level supply voltages. Different topologies with different parameters are compared with the proposed inverter, and the operation of the proposed control scheme is verified with a simulation in Matlab. The prototype of a 31-level inverter is developed in hardware, and the hardware results are discussed.
Keywords:
analog to digital converter, Cascaded Inverter, Reduced Power Switching Devices, Multilevel InverterDownloads
References
M. Jagabar Sathik, N. Prabaharan, S. A. A. Ibrahim, K. Vijaykumar, and F. Blaabjerg, "A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches," International Journal of Circuit Theory and Applications, vol. 48, no. 4, pp. 619–637, 2020. DOI: https://doi.org/10.1002/cta.2732
K. T. Ajmal, K. M. Shafeeque, and B. Jayanand, "A Novel Four Switch Infinite Level Inverter," Journal of Circuits, Systems and Computers, vol. 29, no. 12, Sep. 2020, Art. no. 2050193. DOI: https://doi.org/10.1142/S0218126620501935
J. He, P. Liu, B. Liu, and S. Duan, "An Asymmetric Short-Circuit Fault Ride-Through Strategy Providing Current Limiting and Continuous Voltage Supply for Three-Phase Three-Wire Stand-Alone Inverters," IEEE Access, vol. 8, pp. 211063–211073, 2020. DOI: https://doi.org/10.1109/ACCESS.2020.3038220
M. S. Manoharan, A. Ahmed, and J.-H. Park, "An Improved Model Predictive Controller for 27-Level Asymmetric Cascaded Inverter Applicable in High-Power PV Grid-Connected Systems," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 4, pp. 4395–4405, Sep. 2020. DOI: https://doi.org/10.1109/JESTPE.2019.2935536
S. Yousofi-Darmian and S. Masoud Barakati, "A New Asymmetric Multilevel Inverter With Reduced Number of Components," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 4, pp. 4333–4342, Sep. 2020. DOI: https://doi.org/10.1109/JESTPE.2019.2945757
P. L. Kamani and M. A. Mulla, "A Home-type (H-type) Cascaded Multilevel Inverter with Reduced Device Count: Analysis and Implementation," Electric Power Components and Systems, vol. 47, no. 19–20, pp. 1691–1704, Dec. 2019. DOI: https://doi.org/10.1080/15325008.2019.1660735
V. T. Ha, P. T. Giang, and V. H. Phuong, "T-Type Multi-Inverter Application for Traction Motor Control," Engineering, Technology & Applied Science Research, vol. 12, no. 2, pp. 8321–8327, Apr. 2022. DOI: https://doi.org/10.48084/etasr.4776
P. T. Giang, V. T. Ha, and V. H. Phuong, "Drive Control of a Permanent Magnet Synchronous Motor Fed by a Multi-level Inverter for Electric Vehicle Application," Engineering, Technology & Applied Science Research, vol. 12, no. 3, pp. 8658–8666, Jun. 2022. DOI: https://doi.org/10.48084/etasr.4935
M. A. Jagabar Sathik, S. H. E. Abdel Aleem, R. Kannan, and A. F. Zobaa, "A New Switched DC-Link Capacitor-based Multi-level Converter (SDC2MLC)," Electric Power Components and Systems, vol. 45, no. 9, pp. 1001–1015, May 2017. DOI: https://doi.org/10.1080/15325008.2017.1319434
A. Mokhberdoran and A. Ajami, "Symmetric and Asymmetric Design and Implementation of New Cascaded Multilevel Inverter Topology," IEEE Transactions on Power Electronics, vol. 29, no. 12, pp. 6712–6724, Sep. 2014. DOI: https://doi.org/10.1109/TPEL.2014.2302873
Y. Gopal, K. P. Panda, D. Birla, and M. Lalwani, "Swarm Optimization-Based Modified Selective Harmonic Elimination PWM Technique Application in Symmetrical H-Bridge Type Multilevel Inverters," Engineering, Technology & Applied Science Research, vol. 9, no. 1, pp. 3836–3845, Feb. 2019. DOI: https://doi.org/10.48084/etasr.2397
M. Farhadi Kangarlu and E. Babaei, "Cross-switched multilevel inverter: an innovative topology," IET Power Electronics, vol. 6, no. 4, pp. 642–651, 2013. DOI: https://doi.org/10.1049/iet-pel.2012.0265
Y. Hinago and H. Koizumi, "A Single-Phase Multilevel Inverter Using Switched Series/Parallel DC Voltage Sources," IEEE Transactions on Industrial Electronics, vol. 57, no. 8, pp. 2643–2650, Dec. 2010. DOI: https://doi.org/10.1109/TIE.2009.2030204
J. Dixon, M. Ortuzar, R. Carmi, P. Barriuso, P. Flores, and L. Moran, "Static Var Compensator and Active Power Filter with Power Injection Capability, Using 27-level Inverters and Photovoltaic Cells," in 2006 IEEE International Symposium on Industrial Electronics, Montreal, QC, Canada, Jul. 2006, vol. 2, pp. 1106–1111. DOI: https://doi.org/10.1109/ISIE.2006.295791
V. Pakala and S. Vijayan, "A New DC-AC Multilevel Converter with Reduced Device Count," International Journal of Intelligent Engineering and Systems, vol. 10, no. 3, pp. 391–400, Jun. 2017. DOI: https://doi.org/10.22266/ijies2017.0630.44
W.-K. Choi and F. Kang, "H-bridge based multilevel inverter using PWM switching function," in IN℡EC 2009 - 31st International Telecommunications Energy Conference, Incheon, Korea (South), Jul. 2009, pp. 1–5. DOI: https://doi.org/10.1109/INTLEC.2009.5351886
C. Dhanamjayulu, G. Arunkumar, B. Jaganatha Pandian, and S. Padmanaban, "Design and implementation of a novel asymmetrical multilevel inverter optimal hardware components," International Transactions on Electrical Energy Systems, vol. 30, no. 2, 2020, Art. no. e12201. DOI: https://doi.org/10.1002/2050-7038.12201
D. Shunmugham Vanaja and A. A. Stonier, "A novel PV fed asymmetric multilevel inverter with reduced THD for a grid-connected system," International Transactions on Electrical Energy Systems, vol. 30, no. 4, 2020, Art. no. e12267. DOI: https://doi.org/10.1002/2050-7038.12267
A. Ajami, M. R. Jannati Oskuee, A. Mokhberdoran, and A. Van den Bossche, "Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches," IET Power Electronics, vol. 7, no. 2, pp. 459–466, 2014. DOI: https://doi.org/10.1049/iet-pel.2013.0080
M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, A. Iqbal, and M. A. Memon, "A New Multilevel Inverter Topology With Reduce Switch Count," IEEE Access, vol. 7, pp. 58584–58594, 2019. DOI: https://doi.org/10.1109/ACCESS.2019.2914430
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