Direct ADC Controlled Asymmetric Cascaded Multilevel Inverter
Received: 28 June 2022 | Revised: 8 July 2022 | Accepted: 8 July 2022 | Online: 17 July 2022
Corresponding author: M. J. Shah
This paper presents an asymmetric multi-level inverter with a novel direct ADC control scheme. This scheme does not use a carrier wave or a reference sinusoidal wave to generate gate pulses for power switches, but an Analog to Digital Converter (ADC) to create gate pulses. For n sources, n bit ADC will generate 2n+1-1 levels at the output voltage of the inverter. This scheme uses the ADC output for the gate pulses for power switching devices. In this topology, the inverter comprises a series of connected half-bridges to generate a more significant level. The presented topology uses binary level supply voltages. Different topologies with different parameters are compared with the proposed inverter, and the operation of the proposed control scheme is verified with a simulation in Matlab. The prototype of a 31-level inverter is developed in hardware, and the hardware results are discussed.
Keywords:analog to digital converter, Cascaded Inverter, Reduced Power Switching Devices, Multilevel Inverter
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