Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform

Authors

  • T. Saidani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia | Laboratory of Electronics and Microelectronics, Faculty of Sciences of Monastir, University of Monastir, Tunisia
  • R. Ghodhbani Department of Computer Science, Faculty of Computing and Information Technology, Northern Border University, Saudi Arabia | Laboratory of Electronics and Microelectronics, Faculty of Sciences of Monastir, University of Monastir, Tunisia
Volume: 12 | Issue: 1 | Pages: 8007-8012 | February 2022 | https://doi.org/10.48084/etasr.4615

Abstract

The study conducted in the current paper consists of validating an original design flow for the rapid prototyping of real-time image and video processing applications on FPGAs. A video application for edge detection with Simulink HDL coder and Vivado High-Level Synthesis (HLS) has been designed as if the code was going to be executed on a conventional processor. The developed tools will automatically translate the code into VHDL hardware language using an advanced compilation technique. This amounts to embedding processors on Xilinx Zynq-7000 System on-Chip (SoC) device in an optimal manner. This automated hardware design flow reduces the time to create a prototype since only the high-level description is required. The design of the video edge detection system is implemented on Xilinx Zynq-7000 platform. The result of the implementation gave effective resource utilization and a good frame rate (95 FPS) under 170MHz frequency.

Keywords:

high-level synthesis, automated hardware design, co-design, Xilinx Zynq-7000

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How to Cite

[1]
T. Saidani and R. Ghodhbani, “Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform”, Eng. Technol. Appl. Sci. Res., vol. 12, no. 1, pp. 8007–8012, Feb. 2022.

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