Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform
Received: 12 November 2021 | Accepted: 1 December 2021 | Online: 18 December 2021
Corresponding author: T. Saidani
Abstract
The study conducted in the current paper consists of validating an original design flow for the rapid prototyping of real-time image and video processing applications on FPGAs. A video application for edge detection with Simulink HDL coder and Vivado High-Level Synthesis (HLS) has been designed as if the code was going to be executed on a conventional processor. The developed tools will automatically translate the code into VHDL hardware language using an advanced compilation technique. This amounts to embedding processors on Xilinx Zynq-7000 System on-Chip (SoC) device in an optimal manner. This automated hardware design flow reduces the time to create a prototype since only the high-level description is required. The design of the video edge detection system is implemented on Xilinx Zynq-7000 platform. The result of the implementation gave effective resource utilization and a good frame rate (95 FPS) under 170MHz frequency.
Keywords:
high-level synthesis, automated hardware design, co-design, Xilinx Zynq-7000Downloads
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