Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage-Switched CP-PLL
Published online first on January 14, 2021.
The analysis of the behavior of Charge Pump Phase-Locked Loop (CP-PLL) is a challenging task due to its mixed-signal architecture. Out of its two types, i.e. Current Switched CP-PLL (CSCP-PLL) and Voltage Switched CP-PLL (VSCP-PLL), the prior produces symmetrical pump currents, resulting in an appropriate transient performance to be analyzed. The loop parameters are important to set the gain, target frequency, and assure the stability of the system. The more important is the bandwidth of the loop, which is dependent on the loop filter parameters to perform stable operation and locking time. In this paper, the impact of loop parameter variations on the overall transient behavior of the system is investigated. It has been shown that loop parameters play an important role to ease the design of mixed-signal PLLs.
B. A. A. Antao, F. M. El-Turky, and R. H. Leonowich, "Behavioral modeling phase-locked loops for mixed-mode simulation," Analog Integrated Circuits and Signal Processing, vol. 10, no. 1, pp. 45-65, Jan. 1996. https://doi.org/10.1007/BF00713978
Gardner, Phaselock Techniques, 3rd Edition, 3rd ed. Hoboken, NJ, USA: Wiley-Interscience, 2005. https://doi.org/10.1002/0471732699
R. E. Best, Phase-Locked Loops : Design, Simulation, and Applications, 5th ed. New York, NY, USA: McGraw-Hill Professional, 2003.
D. M. Perisic and M. Bojovic, "Application of Time Recursive Processing for the Development of a Time/Phase Shifter," Engineering, Technology & Applied Science Research, vol. 7, no. 3, pp. 1582-1587, Jun. 2017. https://doi.org/10.48084/etasr.1179
H. E. Taheri, "A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop," Engineering, Technology & Applied Science Research, vol. 7, no. 2, pp. 1473-1477, Apr. 2017. https://doi.org/10.48084/etasr.1099
E. Ali, G. Bhutto, K. Amur, N. Nizamani, R. Khatri, and T. Memon, "Non-linear model of the second order voltage and current switched CP-PLLs," Sindh University Research Journal, vol. 45, no. 4, pp. 737-742, 2013.
P. K. Hanumolu, M. Brownlee, K. Mayaram, and Un-Ku Moon, "Analysis of charge-pump phase-locked loops," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 9, pp. 1665-1674, Sep. 2004. https://doi.org/10.1109/TCSI.2004.834516
C. Hangmann, C. Hedayat, and U. Hilleringmann, "Designing Mixed-Signal PLLs regarding Multiple Requirements taking Non-Ideal Effects into Account," in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), Munich, Germany, Jun. 2019, pp. 1-4. https://doi.org/10.1109/NEWCAS44328.2019.8961261
E. Ali, C. Hangmann, C. Hedayat, F. Haddad, W. Rahajandraibe, and U. Hilleringmann, "Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 3, pp. 347-358, Mar. 2016. https://doi.org/10.1109/TCSI.2015.2512759
F. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980. https://doi.org/10.1109/TCOM.1980.1094619
C. D. Hedayat, A. Hachem, Y. Leduc, and G. Benbassat, "Modeling and Characterization of the 3rd Order Charge-Pump PLL: a Fully Event-driven Approach," Analog Integrated Circuits and Signal Processing, vol. 19, no. 1, pp. 25-45, Apr. 1999. https://doi.org/10.1023/A:1008326315191
E. Ali, W. Rahajandraibe, F. Haddad, C. Hedayat, and C. Hangmann, "Simulative characterization of the stability for second order voltage switched CP-PLL," in 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA, Aug. 2013, pp. 153-156. https://doi.org/10.1109/MWSCAS.2013.6674608
N. Margaris and V. Petridis, "Voltage Pump Phase-Locked Loops," IEEE Transactions on Industrial Electronics, vol. IE-32, no. 1, pp. 41-49, Feb. 1985. https://doi.org/10.1109/TIE.1985.350140
D. Dhar, P. T. M. van Zeijl, D. Milosevic, H. Gao, and P. G. M. Baltus, "Analysis of the Effect of PFD Sampling on Charge-Pump PLL Stability," in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018, pp. 1-5. https://doi.org/10.1109/ISCAS.2018.8351180
A. Mansukhani, "Phase lock loop stability analysis," Applied Microwave and Wireless, vol. 12, no. 2, pp. 30-41, 2000.
MetricsAbstract Views: 203
PDF Downloads: 117
Copyright (c) 2020 Authors
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors who publish with this journal agree to the following terms:
- Authors retain the copyright and grant the journal the right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) after its publication in ETASR with an acknowledgement of its initial publication in this journal.