A Review on Energy Efficient CMOS Digital Logic

B. L. Dokic

Abstract


Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.


Keywords


topology; technology; power consumption; logic delay; CMOS; strong and weak inversion; static and dynamic characteristics; pass logic; adiabatic logic; PL; CPL; PPL; ECRL

Full Text:

PDF

References


R. Sarpeshkar, “Universal principles for ultra low power and energy efficient design”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 59, No.4, pp. 193-198, 2012

J. Rabaey, Low power design essentials, Springer-Verlag, New York, 2009

B. Jovanovic, Analytic model for dynamic consumption evaluation of arithmetic circuits implemented on FPGA, PhD thesis, Elektronski fakultet Nis, 2013

S. R. Nassif, “Waiting for the Post-CMOS Godot”, Int. ACM Great Lakes Symposium on VLSI, Lausanne, Switzerland, 2011

K. Itoh, “A Historical Review of low-power, low-voltage digital MOS circuits development”, IEEE Solid-State Circuits Magazine, Vol. 5, No. 1, pp 27-39, 2013

T. Makimoto, “The Age of the Digital Nomad: Impact of CMOS innovation”, IEEE Solid-State Circuits Magazine, Vol. 5, No. 1,pp 40-47, 2013

Y. Tsividis, C. McAndrew, Operating and modeling o the MOS transistor, Oxford University Press, 2011

B. Dokic, A. Pajkanovic, “Subthreshold operated CMOS analytic model”, INDEL 2012, IX Symposium on Industrial Electronics, Banja Luka, Bosnia and Herzegovina, 2012

A. Wang, B. H. Calhoun, A. P. Chandrakasan, Sub-threshold design for ultra low-power systems, Springer, 2006

L. Nazhandali, B. Zhai, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, T. Austin, D. Blaauw, “Energy optimization of subthreshold-voltage sensor network processes”, ISCA’05, Proc. of the 32nd Int. Symp. on Computer Architecture, Madison, Wisconsin USA, 2005

A. Mishra, R. A. Mishra, “Leakage current minimization in dynamic circuits using sleep switch”, SCES 2012, Students Conference on Engineering and Systems, pp. 1-6, Allahabad, Uttar Pradesh, India, 2012

B. L. Dokic, “Integrated circuits–digital and analog”, Glas Srpski, 1999

P. M. Petkovic, “Design of CMOS integrated circuits with mixed signals”, Elektronski fakultet Nis, 2009

M. Amis, S. Areibi, M. Elmasry, “Design and optimisation of multithreshold CMOS (MTCMOS) circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No 10, pp. 1324 – 1342, 2003

S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, J. Yamada, “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits”, IEEE Journal of Solid-State Circuits, Vol. 32 No. 6, pp. 861–869, 1997

M. Hamada, Y. Ootaguro, T. Kuroda, “Utilizing surplus supplies timing for power reduction”, IEEE Conference on Custom Integrated Circuits, pp. 89-92, San Diego, USA, 2001

C. Piguet, C. Schuster, J. Nagel “Static and Dynamic Power Reduction by Architecture Selection”, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science, Vol. 4148, pp. 659-668, 2006

C. Schuster, J. L. Nagel, C. Piguet, P. A. Farine, “Architectural and Technology Influence on the Optimal Total Power Consumption”, Proceedings of Design, Automation and Test in Europe (DATE '06), pp 13-19, Munich, 2006

W. H. Paik, H. J. Ki, S. W. Kim “Low power logic design using push-pull pass-transistor logics”, International Journal of Electronics, Vol. 84, No. 5, pp. 467-478, 1998

R. K. Yadav, A. K. Rana, S. Chauhan, D. Ranka, K. Yadav, “Adiabatic technique for energy efficient logic circuits design”, International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT 2011), pp 776-780, Tamil Nadu, 2011

V. G. Oklobdzija, D. Maksimovic, L. Fengcheng, “Pass-transistor adiabatic logic using single power-clock supply”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 44, No. 10, pp. 842-846, 1997

A. K. Maurya, G. Kumar, “Energy efficient adiabatic logic for low power VLSI applications”, International Conference on Communication Systems and Network Technologies (CSNT 2011), pp. 460-463, Katra, Jammu, 2011

J. Hu, Q. Chen, “Modelling and near-threshold computing of power-gating adiabatic logic circuits”, Przeglad Elektrotechniczny (Electrical Review), Vol. 88, No. 76, pp. 277-280, 2012

D. Markovic, C. C. Wang, L. P. Alarcon, L. Tsung-Te, J. M. Rabaey, “Ultralow-power design in wear-threshold region”, Proceedings of the IEEE , Vol. 98, No. 2, pp. 237-252, 2010

A. Pajkanovic, T. J. Kazmierski, B. L. Dokic: Adiabatic Digital Circuits Based on Sub-threshold Operation of Pass-transistor and Slowly Ramping Signals, Proceedings of Small Systems Simulation Symposium, pp 48-53, Nis, 2012




eISSN: 1792-8036     pISSN: 2241-4487