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Gowreesrinivas KV, Srinivas S, Samundiswary P. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders. Eng. Technol. Appl. Sci. Res. [Internet]. 2023 Jun. 2 [cited 2024 Jul. 17];13(3):10698-702. Available from: https://etasr.com/index.php/ETASR/article/view/5797