Gowreesrinivas, K. V., Sabbavarapu Srinivas, and Punniakodi Samundiswary. “FPGA Implementation of a Resource Efficient Vedic Multiplier Using SPST Adders”. Engineering, Technology & Applied Science Research 13, no. 3 (June 2, 2023): 10698–10702. Accessed June 30, 2024. https://etasr.com/index.php/ETASR/article/view/5797.