[1]
D. B. L. Quoc, P. L. Vo, P. N. P. Thien, and L. Tran, “High-Performance In-Memory XNOR Computing: A 65 nm 12T SRAM Architecture for Neural Network Acceleration”, Eng. Technol. Appl. Sci. Res., vol. 15, no. 4, pp. 24930–24939, Aug. 2025.