GOWREESRINIVAS, K. V.; SRINIVAS, S.; SAMUNDISWARY , P. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders. Engineering, Technology & Applied Science Research, Greece, v. 13, n. 3, p. 10698–10702, 2023. DOI: 10.48084/etasr.5797. Disponível em: https://etasr.com/index.php/ETASR/article/view/5797. Acesso em: 30 jun. 2024.