PRAVEENA, N.; SHYLASHREE, N. Low Power High Speed Finfet Dram Cell and 4x4 Array Design Using the Sleep Transistor Technique. Engineering, Technology & Applied Science Research, Greece, v. 16, n. 2, p. 32955–32961, 2026. DOI: 10.48084/etasr.15183. Disponível em: https://etasr.com/index.php/ETASR/article/view/15183. Acesso em: 20 apr. 2026.