FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders
Received: 19 February 2023 | Revised: 27 March 2023 | Accepted: 29 March 2023 | Online: 2 June 2023
Corresponding author: K. V. Gowreesrinivas
Abstract
Nowadays, the requirement for very high-speed operations in processors constantly increases. Multiplication is a crucial operation in high power-consuming processes such as image and signal processing. The main characteristics of a multiplier are good accuracy, speed, reduction in area, and little power consumption. Speed plays a major role in multiplication operations, and an increase in speed can be obtained by reducing the number of steps involved in the computation process. Since a multiplier has the largest delay among the basic blocks in a digital system, the critical path is determined by it. Furthermore, the multiplier consumes more area and dissipates more power. Hence, designing multipliers that offer high speed, lower power consumption, less area, or a combination of them is of prime concern. Hence, an attempt is made in this paper to achieve the above design metrics using a Spurious Power Suppression Technique (SPST) adder. A resource-efficient SPST-based Vedic multiplier is developed and implemented using Artix 7 FPGA and is finally compared with the ripple carry adder-based Vedic multiplier.
Keywords:
vedic multiplier, Urdhva Triyakbhyam, Spurious Power Suppression Technique (SPST), Verilog, Artix7Downloads
References
M. Ramalatha, K. D. Dayalan, P. Dharani, and S. D. Priya, "High speed energy efficient ALU design using Vedic multiplication techniques," in 2009 International Conference on Advances in Computational Tools for Engineering Applications, Beirut, Lebanon, Jul. 2009, pp. 600–603. DOI: https://doi.org/10.1109/ACTEA.2009.5227842
Y. Bansal and C. Madhu, "A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders," Computers & Electrical Engineering, vol. 49, pp. 39–49, Jan. 2016. DOI: https://doi.org/10.1016/j.compeleceng.2015.11.006
R. K. Barik, M. Pradhan, and R. Panda, "Time efficient signed Vedic multiplier using redundant binary representation," The Journal of Engineering, vol. 2017, no. 3, pp. 60–68, Mar. 2017. DOI: https://doi.org/10.1049/joe.2016.0376
Y. Bansal, C. Madhu, and P. Kaur, "High speed vedic multiplier designs-A review," in 2014 Recent Advances in Engineering and Computational Sciences (RAECS), Chandigarh, India, Mar. 2014. DOI: https://doi.org/10.1109/RAECS.2014.6799502
A. Kumar and A. Raman, "Low power ALU design by ancient mathematics," in 2010 The 2nd International Conference on Computer and Automation Engineering (ICCAE), Singapore, Oct. 2010, vol. 5, pp. 862–865. DOI: https://doi.org/10.1109/ICCAE.2010.5451892
D. Jaina, K. Sethi, and R. Panda, "Vedic Mathematics Based Multiply Accumulate Unit," in 2011 International Conference on Computational Intelligence and Communication Networks, Gwalior, India, Jul. 2011, pp. 754–757. DOI: https://doi.org/10.1109/CICN.2011.167
R. K. Bathija, R. S. Meena, S. Sarkar, and R. Sahu, "Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics," International Journal of Computer Applications, vol. 59, no. 6, pp. 41–44, Dec. 2012. DOI: https://doi.org/10.5120/9556-4016
S. Anjana, C. Pradeep, and P. Samuel, "Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics," Procedia Computer Science, vol. 46, pp. 1294–1302, Jan. 2015. DOI: https://doi.org/10.1016/j.procs.2015.01.054
N. H. Nguyen, S. A. Khan, C.-H. Kim, and J.-M. Kim, "A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms," Microprocessors and Microsystems, vol. 60, pp. 96–106, Jul. 2018. DOI: https://doi.org/10.1016/j.micpro.2018.04.003
Y.-H. Seo and D.-W. Kim, "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp. 201–208, Oct. 2010. DOI: https://doi.org/10.1109/TVLSI.2008.2009113
W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, "Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing," IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435–1441, Dec. 2017. DOI: https://doi.org/10.1109/TC.2017.2672976
A. Mittal, A. Nandi, and D. Yadav, "Comparative study of 16-order FIR filter design using different multiplication techniques," IET Circuits, Devices & Systems, vol. 11, no. 3, pp. 196–200, 2017. DOI: https://doi.org/10.1049/iet-cds.2016.0146
D. M. Perisic and M. Bojovic, "Application of Time Recursive Processing for the Development of a Time/Phase Shifter," Engineering, Technology & Applied Science Research, vol. 7, no. 3, pp. 1582–1587, Jun. 2017. DOI: https://doi.org/10.48084/etasr.1179
D. M. Perisic, A. C. Zoric, and Z. Gavric, "A Frequency Multiplier Based on Time Recursive Processing," Engineering, Technology & Applied Science Research, vol. 7, no. 6, pp. 2104–2108, Dec. 2017. DOI: https://doi.org/10.48084/etasr.1499
D. M. Perisic, V. Petrovic, and B. Kovacevic, "Frequency Locked Loop Based on the Time Nonrecursive Processing," Engineering, Technology & Applied Science Research, vol. 8, no. 5, pp. 3450–3455, Oct. 2018. DOI: https://doi.org/10.48084/etasr.2256
K.-H. Chen and Y.-S. Chu, "A Low-Power Multiplier With the Spurious Power Suppression Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 7, pp. 846–850, Jul. 2007. DOI: https://doi.org/10.1109/TVLSI.2007.899242
H. S. K. Puttam, P. S. Rao, and N. V. G. Prasad, "Implementation of Low Power and High Speed Multiplier- Accumulator Using SPST Adder and Verilog," International Journal of Modern Engineering Research, vol. 2, no. 5, pp. 3390–3397, 2012.
A. Prashanth, R. P. Waran, and S. K. and S. Pawar, "Low Power High Speed based Various Adder Architectures using SPST," Indian Journal of Science and Technology, vol. 9, no. 29, pp. 1–3, May 2016. DOI: https://doi.org/10.17485/ijst/2016/v9i29/93197
V. S. Narayan, S. M. Pratima, V. S. Saroja, and R. M. Banakar, "High Speed Low Power VLSI Architecture for SPST Adder Using Modified Carry Look Ahead Adder," in Proceedings of International Conference on Advances in Computing, New Delhi, India, 2012, pp. 461–466. DOI: https://doi.org/10.1007/978-81-322-0740-5_56
A. Purna Ramesh, A. V. N. Tilak, and A. M. Prasad, "Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog," International Journal of VLSI Design & Communication Systems, vol. 3, no. 3, pp. 107–118, Jul. 2012. DOI: https://doi.org/10.5121/vlsic.2012.3310
Downloads
How to Cite
License
Copyright (c) 2023 K. V. Gowreesrinivas, Srinivas Sabbavarapu, Punniakodi Samundiswary
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors who publish with this journal agree to the following terms:
- Authors retain the copyright and grant the journal the right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) after its publication in ETASR with an acknowledgement of its initial publication in this journal.
