A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader
Received: 15 July 2022 | Revised: 9 August 2022 | Accepted: 10 August 2022 | Online: 2 October 2022
Corresponding author: J. Sampe
An All-Digital Phase-Locked Loop (ADPLL) is an architecture that is widely employed in the communication system due to the advancement of the Complementary Metal-Oxide-Semiconductor (CMOS) technology process. A 2.4GHz Radio Frequency Identification (RFID) system needs a frequency synthesizer in the local oscillator architecture of the transceiver to generate a stable frequency tuning range Therefore, in this paper, a Digital Phase-Frequency Detector (DPFD) is designed to achieve the phase and frequency acquisition in the ADPLL system. The proposed DPFD is divided into two main parts, the first is the Phase Detector (PD) and the second is the Frequency Detector (FD). The PD has managed to detect the presence of the phase difference by recognizing two different input signals. The FD, on the other hand, is capable to detect the higher frequency by identifying the output signals from the PD in digital formation. In addition, a control unit module is developed to control and adjust the Preset Word (PW) for the system by using a binary search scheme. Comparison results show that the final value of the PW from the simulation is the same as from the manual calculation (theoretical values). The digital PFD and the PW control modules are designed and simulated by using Verilog HDL code. These two designed modules will be integrated into the targeted ADPLL to achieve fast locking performance and ultra-low power for Ultra-High Frequency (UHF) RFID applications.
Keywords:RFID, all-digital PLL, ADPLL, digital PFD, frequency synthesizer, local oscillator, binary search
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