A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader

Authors

  • S. N. Ishak Institute of Microengineering & Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, Malaysia
  • J. Sampe Institute of Microengineering & Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, Malaysia
  • N. A. Nayan Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia, Malaysia
  • Z. Yusoff Faculty of Engineering, Multimedia University, Malaysia
Volume: 12 | Issue: 5 | Pages: 9379-9387 | October 2022 | https://doi.org/10.48084/etasr.5202

Abstract

An All-Digital Phase-Locked Loop (ADPLL) is an architecture that is widely employed in the communication system due to the advancement of the Complementary Metal-Oxide-Semiconductor (CMOS) technology process. A 2.4GHz Radio Frequency Identification (RFID) system needs a frequency synthesizer in the local oscillator architecture of the transceiver to generate a stable frequency tuning range Therefore, in this paper, a Digital Phase-Frequency Detector (DPFD) is designed to achieve the phase and frequency acquisition in the ADPLL system. The proposed DPFD is divided into two main parts, the first is the Phase Detector (PD) and the second is the Frequency Detector (FD). The PD has managed to detect the presence of the phase difference by recognizing two different input signals. The FD, on the other hand, is capable to detect the higher frequency by identifying the output signals from the PD in digital formation. In addition, a control unit module is developed to control and adjust the Preset Word (PW) for the system by using a binary search scheme. Comparison results show that the final value of the PW from the simulation is the same as from the manual calculation (theoretical values). The digital PFD and the PW control modules are designed and simulated by using Verilog HDL code. These two designed modules will be integrated into the targeted ADPLL to achieve fast locking performance and ultra-low power for Ultra-High Frequency (UHF) RFID applications.

Keywords:

RFID, all-digital PLL, ADPLL, digital PFD, frequency synthesizer, local oscillator, binary search

Downloads

Download data is not yet available.

References

G. Maniam, J. Sampe, R. Jaafar, and M. Ibrahim, "Smart Monitoring System for Chronic Kidney Disease Patients based on Fuzzy Logic and IoT," International Journal of Advanced Computer Science and Applications, vol. 13, no. 2, pp. 324–333, Jan. 2022. DOI: https://doi.org/10.14569/IJACSA.2022.0130238

N. H. Mohd Yunus, J. Sampe, J. Yunas, A. Pawi, and Z. A. Rhazali, "MEMS based antenna of energy harvester for wireless sensor node," Microsystem Technologies, vol. 26, no. 9, pp. 2785–2792, Sep. 2020. DOI: https://doi.org/10.1007/s00542-020-04842-5

N. H. Mohd Yunus, J. Yunas, A. Pawi, Z. A. Rhazali, and J. Sampe, "Investigation of Micromachined Antenna Substrates Operating at 5 GHz for RF Energy Harvesting Applications," Micromachines, vol. 10, no. 2, Feb. 2019, Art. no. 146. DOI: https://doi.org/10.3390/mi10020146

K. Mekki, O. Necibi, C. Boussetta, and A. Gharsallah, "Miniaturization of Circularly Polarized Patch Antenna for RFID Reader Applications," Engineering, Technology & Applied Science Research, vol. 10, no. 3, pp. 5655–5659, Jun. 2020. DOI: https://doi.org/10.48084/etasr.3445

T. N. T. Mohamad, J. Sampe, and D. D. Berhanuddin, "Architecture of Micro Energy Harvesting Using Hybrid Input of RF, Thermal and Vibration for Semi-Active RFID Tag," Engineering Journal, vol. 21, no. 2, pp. 183–197, Mar. 2017. DOI: https://doi.org/10.4186/ej.2017.21.2.183

C. Bredendiek et al., "A 61-GHz SiGe Transceiver Frontend for Energy and Data Transmission of Passive RFID Single-Chip Tags With Integrated Antennas," IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2441–2453, Sep. 2018. DOI: https://doi.org/10.1109/JSSC.2018.2843348

M. Faseehuddin, M. A. Albrni, J. Sampe, and S. H. M. Ali, "Novel VDBA based universal filter topologies with minimum passive components:," Journal of Engineering Research, vol. 9, no. 3B, pp. 110–130, Sep. 2021. DOI: https://doi.org/10.36909/jer.v9i3B.8781

E. Ali, D. Narwani, A. M. Bughio, N. Nizamani, S. H. Siyal, and A. R. Khatri, "Analyzing the Impact of Loop Parameter Variations on the Transient Response of Second Order Voltage-Switched CP-PLL," Engineering, Technology & Applied Science Research, vol. 11, no. 1, pp. 6687–6690, Feb. 2021. DOI: https://doi.org/10.48084/etasr.3969

J. Sampe, M. Faseehuddin, and S. H. M. Ali, "Design of ultra-low voltage CCII utilizing level shifting technique and a dual mode multifunction universal filter as an application," Journal of Engineering Research, vol. 6, no. 2, pp. 155–175, Sep. 2018.

J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412–422, Apr. 1995. DOI: https://doi.org/10.1109/4.375961

J. Bae, S. Radhapuram, I. Jo, T. Kihara, and T. Matsuoka, "A low-voltage design of controller-based ADPLL for implantable biomedical devices," in IEEE Biomedical Circuits and Systems Conference, Atlanta, GA, USA, Oct. 2015, pp. 1–4. DOI: https://doi.org/10.1109/BioCAS.2015.7348405

M.-L. Lin, S.-C. Huang, and J.-C. Liu, "Digital-only PLL with adaptive search step," International Journal of Electronics, vol. 101, no. 6, pp. 865–876, Jun. 2014. DOI: https://doi.org/10.1080/00207217.2014.896036

H.-J. Hsu and S.-Y. Huang, "A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 1, pp. 165–170, Jan. 2011. DOI: https://doi.org/10.1109/TVLSI.2009.2030410

M. Kumm, H. Klingbeil, and P. Zipf, "An FPGA-Based Linear All-Digital Phase-Locked Loop," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2487–2497, Sep. 2010. DOI: https://doi.org/10.1109/TCSI.2010.2046237

W. Liu, W. (R.) Li, P. Ren, C. L. Lin, S. Zhang, and Y. Wang, "An 11-bit and 39 ps resolution time-to-digital converter for ADPLL in digital television," International Journal of Electronics, vol. 97, no. 4, pp. 381–388, Apr. 2010. DOI: https://doi.org/10.1080/00207210903325237

K. Okuno, S. Izumi, K. Masaki, H. Kawaguchi, and M. Yoshimoto, "A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E98.A, no. 12, pp. 2592–2599, 2015. DOI: https://doi.org/10.1587/transfun.E98.A.2592

G. Yu, Y. Wang, H. Yang, and H. Wang, "Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting," IET Circuits, Devices & Systems, vol. 4, no. 3, pp. 207–217, May 2010. DOI: https://doi.org/10.1049/iet-cds.2009.0173

A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, "A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration," in IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, Feb. 2011, pp. 92–94. DOI: https://doi.org/10.1109/ISSCC.2011.5746233

J. Liu et al., "15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider," in IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA, Feb. 2014, pp. 268–269. DOI: https://doi.org/10.1109/ISSCC.2014.6757429

C.-C. Chung and C.-Y. Ko, "A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2300–2311, Jul. 2011. DOI: https://doi.org/10.1109/JSSC.2011.2160789

S. N. Ishak, J. Sampe, F. H. Hashim, and M. Faseehuddin, "Digital Phase-Frequency Detector in All-Digital PLL-based Local Oscillator for Radio Frequency Identification System Transceiver," in 18th International Colloquium on Signal Processing & Applications, Selangor, Malaysia, Dec. 2022, pp. 231–236. DOI: https://doi.org/10.1109/CSPA55076.2022.9781829

I.-C. Hwang, S.-H. Song, and S.-W. Kim, "A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition," IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1574–1581, Jul. 2001. DOI: https://doi.org/10.1109/4.953487

C.-C. Chung, W.-S. Su, and C.-K. Lo, "A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 408–412, Jan. 2016. DOI: https://doi.org/10.1109/TVLSI.2015.2407370

J. K. Sahani, A. Singh, and A. Agarwal, "A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC," AEU - International Journal of Electronics and Communications, vol. 124, Sep. 2020, Art. no. 153344. DOI: https://doi.org/10.1016/j.aeue.2020.153344

W.-B. Yang, H.-H. Wang, H.-I. Chang, and Y.-L. Lo, "A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications," Japanese Journal of Applied Physics, vol. 59, no. SG, Nov. 2020, Art. no. SGGL08. DOI: https://doi.org/10.35848/1347-4065/ab7276

B. Zhao and D. L. Yan, "A low-power digital design of all digital PLL for 2.4G wireless communication applications," in International Symposium on Integrated Circuits, Singapore, Singapore, Dec. 2016, pp. 1–4. DOI: https://doi.org/10.1109/ISICIR.2016.7829674

L. Ferreira, M. Moreira, B. Souza, S. Ferreira, F. Baumgratz, and S. Bampi, "Review on the Evolution of Low-power and Highly-linear Time-to-Digital Converters - TDC," in 11th Latin American Symposium on Circuits & Systems, San Jose, Costa Rica, Feb. 2020, pp. 1–4. DOI: https://doi.org/10.1109/LASCAS45839.2020.9068950

S. N. Ishak, J. Sampe, Z. Yusoff, and M. Faseehuddin, "All-Digital Phase Locked Loop (ADPLL) Topologies For RFID System Application: A Review," Jurnal Teknologi (Sciences and Engineering), vol. 84, no. 1, pp. 219–230, 2021. DOI: https://doi.org/10.11113/jurnalteknologi.v84.17123

J.-M. Lin and C.-Y. Yang, "A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 10, pp. 2411–2422, Jul. 2015. DOI: https://doi.org/10.1109/TCSI.2015.2477575

H. E. Taheri, "A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop," Engineering, Technology & Applied Science Research, vol. 7, no. 2, pp. 1473–1477, Apr. 2017. DOI: https://doi.org/10.48084/etasr.1099

X. Deng, H. Li, and M. Zhu, "A Novel Fast-Locking ADPLL Based on Bisection Method," Electronics, vol. 10, no. 12, Jan. 2021, Art. no. 1382. DOI: https://doi.org/10.3390/electronics10121382

A. Ersöz and M. Kurban, "Bisection Method and Algorithm for Solving the Electrical Circuits," presented at the 2nd International Eurasian Conference on Mathematical Sciences and Applications, Sarajevo, Bosnia-Herzegovina, Aug. 2013.

T. Azadmousavi, M. Azadbakht, E. Najafi Aghdam, and J. Frounchi, "A novel zero dead zone PFD and efficient CP for PLL applications," Analog Integrated Circuits and Signal Processing, vol. 95, no. 1, pp. 83–91, Apr. 2018. DOI: https://doi.org/10.1007/s10470-018-1118-4

P. Muppala, S. Ren, and G. Y.-H. Lee, " esign of high-frequency wide-range all digital phase locked loop in 90 nm CMOS," Analog Integrated Circuits and Signal Processing, vol. 75, no. 1, pp. 133–145, Apr. 2013. DOI: https://doi.org/10.1007/s10470-013-0043-9

G. Yu, Y. Wang, H. Yang, and H. Wang, "A fast-locking all-digital phase-locked loop with a novel counter-based mode switching controller," in IEEE Region 10 Conference, Singapore, Singapore, Jan. 2009, pp. 1–5. DOI: https://doi.org/10.1109/TENCON.2009.5396168

Downloads

How to Cite

[1]
S. N. Ishak, J. Sampe, N. A. Nayan, and Z. Yusoff, “A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader”, Eng. Technol. Appl. Sci. Res., vol. 12, no. 5, pp. 9379–9387, Oct. 2022.

Metrics

Abstract Views: 331
PDF Downloads: 185

Metrics Information
Bookmark and Share