A Power-Aware Real-Time System for Multi-Video Treatment on FPGA with Dynamic Partial Reconfiguration and Voltage Scaling
Received: 21 May 2022 | Revised: 10 June 2022 | Accepted: 13 June 2022 | Online: 7 August 2022
Corresponding author: L. Kechiche
Abstract
As the energy consumption is an evaluating factor for System-On-Chip (SOC) design, this paper presents a power-aware architecture for a real-time multi-video system on FPGA. This architecture aims to optimize power consumption for a multi-video system on ARM-based architectures. The proposed architecture uses dynamic reconfiguration and voltage scaling to create a power-aware system for real-time multi-video processing with minimal power dissipation. Dynamic partial reconfiguration was used to optimize the utilization of resources and reduce dynamic power consumption. Voltage scaling was also used to optimize dynamic power consumption, by configuring the blocks to use the minimum necessary voltage for normal operating conditions. The proposed architecture focused on the Zynq platform. The results showed power savings of up to 70% concerning performance and real-time constraints.
Keywords:
power consumption, ZYNQ, ARM A9, dynamic partial reconfiguration, voltage scalingDownloads
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