Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor
Abstract
The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.
Keywords:
1-bit full adder, CNTFET, PDP, low power, HSPICEDownloads
References
C. Venkatesan, S. M. Thabsera, M. G. Sumitrha, M. Suriya, “Analysis of 1-bit full adder using different techniques in Cadence 45nm technology”, 5th International Conference on Advanced Computing & Communication Systems, Coimbatore, India, March 15-16, 2019 DOI: https://doi.org/10.1109/ICACCS.2019.8728449
N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI design: a system perspective, Addison-Wesley, 1988
C. H. Chang, J. Gu, M. Zhang, “A review of 0.18-µm full adder performances for tree structured arithmetic circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp. 686-695, 2005 DOI: https://doi.org/10.1109/TVLSI.2005.848806
M. A Aguirre-Hernandez, M. Linares-Aranda, “CMOS full-adders for energy-efficient arithmetic applications”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems ,Vol. 19, No. 4, pp. 718-721, 2011 DOI: https://doi.org/10.1109/TVLSI.2009.2038166
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, “Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2001-2008, 2015 DOI: https://doi.org/10.1109/TVLSI.2014.2357057
Y. S. Mehrabani, M. Eshghi, “Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 11, pp. 3268-3281, 2016 DOI: https://doi.org/10.1109/TVLSI.2016.2540071
K. S. Jitendra, A. Srinivasulu, B. P. Singh, “A new low-power full adder cell for low voltage using CNFETs”, IEEE 9th International Conference on Electronics, Computers and Artificial Intelligence, Targoviste, Romania, June 29-July 1, 2017 DOI: https://doi.org/10.1109/ECAI.2017.8166425
M. Maleknejad, S. Mohammadi, K. Navi, H. R. Naji, M. Hosseinzadeh, “A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications”, International Journal of Electronics, Vol. 105, No. 10, pp. 1753-1768, 2018 DOI: https://doi.org/10.1080/00207217.2018.1477205
K. S. Jitendra, A. Srinivasulu, R. Kumawat, “A low power - high speed CNTFETs based full adder cell with overflow detection”, Micro and Nanosystems, Vol. 11, No. 1, pp. 80-87, 2019 DOI: https://doi.org/10.2174/1876402911666190211154634
M. H. Moaiyeri, R. F. Mirrzae, K. Navi, A. Momeni, “Design and analysis of a high-performance CNFET-based Full Adder”, International Journal of Electronics, Vol. 99, No. 1, pp. 113-130, 2012
Y. M. Lin, J. Appenzeller, P. Avouris, “Novel structures enabling bulk switching in carbon nanotube FETs”, Device Research Conference, 62nd DRC., Notre Dame, USA, June 21-23, 2004
M. Moradi, R. F. Mirzaee, M. H. Moaiyeri, K. Navi, “An applicable high-efficient CNTFET -based full adder cell for practical environments”, 16th CSI International Symposium on Computer Architecture and Digital Systems, Shiraz, Iran, May 2-3, 2012 DOI: https://doi.org/10.1109/CADS.2012.6316411
R. F. Mirzaee, M. H. Moaiyeri, H. Khorsand, K. Navi, “A new robust and high-performance hybrid full adder cell”, Journal of Circuits, Systems, and Computers, Vol. 20, No. 4, pp. 641-655, 2011 DOI: https://doi.org/10.1142/S0218126611007517
M. H. Moaiyeri, R. F. Mirzaee, K. Navi, A. Momeni, “Design and analysis of a high-performance CNFET-based full adder”, International Journal of Electronics, Vol. 99, No. 1, pp. 113-130, 2012 DOI: https://doi.org/10.1080/00207217.2011.623269
M. H. Ghadiry, A. A. Manaf, M. T. Ahmadi, H. Sadeghi, M. N. Senejani, “Design and analysis of a new carbon nanotube full adder cell”, Journal of Nanomaterials, Vol. 2011, Article ID. 906237, 2011 DOI: https://doi.org/10.1155/2011/906237
J. F. Lin, Y. T. Hwang, M. H. Sheu, C. C. Ho, “A novel high speed and energy efficient 10-transistor full adder design”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, No. 5 , pp. 1050–1059, 2007 DOI: https://doi.org/10.1109/TCSI.2007.895509
B. L. Dokic, “A review on energy efficient CMOS digital logic”, Engineering, Technology & Applied Science Research, Vol. 3, No. 6, pp. 552-561, 2013 DOI: https://doi.org/10.48084/etasr.389
N. Zhuang, H. Wu, “A new design of the CMOS full adder”, IEEE Journal of Solid-State Circuits ,Vol. 27, No. 5, 840–844., 1992 DOI: https://doi.org/10.1109/4.133177
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