A Gain Programmable Analog Divider Circuit Based on a Data Converter

  • S. N. Asl Department of Electrical Engineering, Damghan Branch, Islamic Azad University, Damghan, Iran
  • M. Tarkhan Department of Electrical Engineering, Zahedan Branch, Islamic Azad University, Zahedan, Iran
  • M. S. Nia Department of Electrical Engineering, Damghan Branch, Islamic Azad University, Damghan, Iran
Volume: 7 | Issue: 6 | Pages: 2251-2255 | December 2017 | https://doi.org/10.48084/etasr.1436


Analog dividers are widely used in analog systems. Analog realization of such circuits suffer from limited dynamic range and non-linearity issues, therefore, extra circuitry should be required to compensate these types of shortcomings. In this paper a gain controllable, analog divider is proposed based on data converters. Our circuit can be implemented both in current and voltage mode by selecting proper architectures. The resolution, power consumption and operation speed can be controlled by proper selecting of components. Another advantage of our circuit is its gain programmability. Moreover, the gain can be adjusted independently based on the relationship between input signals. Our proposed method offers two different gain control abilities, one for situation that the numerator signal is bigger than the denominator, and another gain is applied when the denominator is larger than the numerator. As a result, no extra amplifier is required for signal amplification. Moreover, the input and output signal nature can be chosen arbitrarily in this circuit, i.e. input signal may be a voltage signal while the output signal is current. Simulation results from SPICE confirm the proper operation of the circuit.

Keywords: analog divider, data converter based divider, gain adjustable analog divider, wide dynamic range analog divider, mixed signal divider


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M. T. Abuelma’atti, M. A. Alabsi, “A CMOS Analog Cell and its applications in analog signal processing”, International Journal of Electronics, Vol. 93, No. 4, pp. 251-267, 2006 DOI: https://doi.org/10.1080/00207210500519513

H. Asiaban, E. Farshidi, “A new true RMS-to-DC converter in CMOS technology”, International Journal of Electrical and Computer Engineering, Vol. 71, No. 11, pp. 1592-1595, 2010

K. Bult, H. Wallinga, “A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation”, IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, pp. 357-365, 1979 DOI: https://doi.org/10.1109/JSSC.1987.1052733

M. Dei, N. Nizza, M. Piotto, P. Bruschi, “A voltage controlled CMOS current divider with linear characteristic”, Analog Integrated Circuits and Signal Processing, Vol. 58, No. 1, pp. 43-47, 2009 DOI: https://doi.org/10.1007/s10470-008-9211-8

C. Dualibe, M. Verleysen, P. Jespers, “Two-quadrant CMOS analogue divider”, Electronic Letters, Vol. 34, No. 12, pp. 1164–1165, 1998 DOI: https://doi.org/10.1049/el:19980861

E. Farshidi, H. Asiaban, “A new true RMS-to-DC converter using up-down translinear loop in CMOS technology”, Analog Integrated Circuits and Signal Processing, Vol. 70, No. 3, pp. 385-390, 2012 DOI: https://doi.org/10.1007/s10470-011-9691-9

I. Baturone, S. Sanchez-Solano, J. L. Huertas, “A CMOS current-mode multiplier/divider circuit”, , IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 520–523, 2002

M. A. Al-Absi, “Low-voltage and low-power CMOS current-mode divider and 1/x circuit”, International Conference on Electronic Devices, Systems and Applications, pp. 245-247, 2010 DOI: https://doi.org/10.1109/ICEDSA.2010.5503064

M. Barbaro, G. N. Angotzi, “Compact, low-power, analogue building blocks derived from MOSFETs translinear loops”, IEEE International Conference on Electronics, Circuits, and Systems, pp. 592-595, 2006 DOI: https://doi.org/10.1109/ICECS.2006.379858

C.-C. Chang, S.-I. Liu, “Weak inversion four-quadrant multiplier and two-quadrant divider”, Electronic Letters, Vol. 34, No. 22, pp. 2079-2080, 1998 DOI: https://doi.org/10.1049/el:19981496

A. Mahmoudi, A. Khoei, K. H. Hadidi, “A novel current-mode micropower four quadrant CMOS analog multiplier/divider”, IEEE Conference on Electron Devices and Solid-State Circuits, pp. 321-324, 2007 DOI: https://doi.org/10.1109/EDSSC.2007.4450127

E. Rodriguez-Villegas, J. Alam, “Ultra low power four-quadrant multiplier/two-quadrant divider circuit using FGMOS”, 49th International Midwest Symposium on Circuits and Systems, pp. 64-68, 2006 DOI: https://doi.org/10.1109/MWSCAS.2006.382209

A. Taji, A. Khoei, K. Hadidi, M. Padash, “Low-voltage and low-power consumption 0.35um CMOS voltage-mode defuzzifier”, International Conference on Electronic Devices, Systems, and Applications, pp. 161-164, 2011 DOI: https://doi.org/10.1109/ICEDSA.2011.5959081

A. Cichocki, R. Unbehauen, “A novel switched-capacitor four-quadrant analog multiplier-divider and some of its applications”, IEEE Transactions on Instrumentation and Measurement, Vol. IM-35, No. 2, pp. 156-162, 1986 DOI: https://doi.org/10.1109/TIM.1986.6499083

M. S. Piedade, A. Pinto, “A new multiplier-divider circuit based on switched capacitor data converters”, IEEE International Symposium on Circuits and Systems, pp. 2224–2227, 1990

Y.-J. Chen, K.-H. Chang, C.-C. Hsieh, “A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 51, No. 2, 2016 DOI: https://doi.org/10.1109/JSSC.2015.2492781

Y. Choi, Y.-B. Kim, I.-S. Jung, “A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration”, IEEE 25th North Atlantic Test Workshop, pp. 1-5, 2016 DOI: https://doi.org/10.1109/NATW.2016.9

A. Elkafrawy, J. Anders, M. Ortmanns, “A 10-bit 150MS/s current mode SAR ADC in 90nm CMOS”, 11th Conference on Ph.D. Research in Microelectronics and Electronics, pp. 274-277, 2015 DOI: https://doi.org/10.1109/PRIME.2015.7251388

K. Ragab, N. Sun, “A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS”, 42nd European Solid-State Circuits Conference, pp. 417-420, 2016 DOI: https://doi.org/10.1109/ESSCIRC.2016.7598330

Y. Song, Z. Xue, Y. Xie, S. Fan, L. Geng, “A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC with Incremental Converting Algorithm for Energy Efficient Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 63, No. 4, pp. 449-458, 2016 DOI: https://doi.org/10.1109/TCSI.2016.2528080

Y. Tao, Y. Lian, “A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-channel neural recording”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 2, pp. 366-375, 2015 DOI: https://doi.org/10.1109/TCSI.2014.2360762


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