A Review on Energy Efficient CMOS Digital Logic

Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.


INTRODUCTION
Designers of digital circuits are confronted with two often conflicting demands: how to achieve higher operating speeds and lower energy consumption.Usually, the same circuit family could not satisfy both demands at the same time, i.e. high-speed circuits have high level of consumption and vice versa.That's how series of integrated circuits called low-power circuits or high-speed circuits were created.Optimally designed digital system includes a variety of different series of the same integrated circuits' family.
Today, as the whole digital system is manufactured as a single integrated circuit, the designing problem is reduced to the choice of a design that can ensure maximum energy efficiency.That implies the design with minimum power consumption inside the specified frequency range or maximum operating speed for a given energy consumption level.The usage of low-power sources of power supply, which collect their primary energy from the environment, has increased lately.Thus, the art of design of low power circuits is brought down to the selection of optimal (intelligent) solutions that will reduce the speed of information processing as much as possible, without violating certain system characteristics.Such an optimal project implies the decomposition of the system architecture, good choice of the circuit topology that will provide the optimal synthesis of different functions in the defined architecture, and good choice of the circuit design technology.This requires the designer to be familiar with components, circuits and systems.Consumption of each system is determined using the following five guidelines of each project: given task, technology, circuit topology, operating speed and accuracy.Since these five guidelines can be placed on the fingers of one hand, they are known as "low-power hand" [1].Therefore, optimization of energy consumption is a multidimensional problem that requires taking into consideration the level of consumption at each stage of the VLSI integrated circuit design.The biggest savings of electrical energy consumption (10 to 20 times), with least waste of time (at the level of a minute) is done in the early stages of designing, in which the project is presented as a set of abstract communication tasks [2].The application of optimization techniques and consumption provides an estimation at each project stage, leading to optimal consumption project [3].At lower levels of the design (transistor, deployment and connectivity), possible energy savings are significantly lower (10 to 20%), and time estimation can last for days, because the project is presented with all detail.Thus, it is necessary to process a very large amount of data [3].CMOS digital circuits' technology based on silicon will most likely be dominant for the next twenty years or more [4,5,6], with standard low power consumption, technology for reducing the transistor size to a scale of about ten nanometers and operating speed in the GHz domain.During the last ten years, more attention from researchers as well as manufacturer of integrated circuits is paid to digital CMOS circuits operating in the sub-threshold (weak inversion) regime.Supply voltage in this regime is lower than the threshold voltage V t of MOS transistors (V dd <V t ) and is about a few hundred millivolts.Thanks to that fact, the dynamic consumption level is significantly reduced in regard to CMOS circuits operating in the strong inversion regime.Since the operating area in the sub-threshold regime is overlapped with the area of a disconnected transistors in strong inversion regime, current ratio in on and off the state has been significantly reduced.Consequently, CMOS circuit logic delay in the sub-threshold regime is several orders of magnitude higher.
Designers of CMOS digital devices, especially portable ones, have a challenging requirement: how to ensure high processing power and very complex functionality along with low power consumption.Certainly part of the solution is a proper choice of CMOS technology as well as weak and strong inversion regime operating areas.
Although MOS transistor static characteristics in weak inversion and strong inversion regimes are functionally very different, it will be shown that there is an absolute analogy in the behavior and functional dependency of CMOS circuit parameters in those regimes.Thanks to that, design techniques of more complex CMOS circuits are the same in sub-threshold and strong inversion regime.This fact considerably facilitates designer's work of CMOS circuit in a sub-threshold regime and enables faster development.
Optimal consumption generally does not mean minimal consumption.Minimal consumption and minimal logic delay are mutually opposite requirements.Taking into account only the minimization of consumption, a project with unacceptable logic delay could be delivered.The consumption as well as the logic delay of CMOS circuit depends on MOS transistor threshold voltage V t and supply voltage V dd .Because of that, one part of this paper is devoted to consumption optimization techniques in systems with multiple levels of V t and V dd .Specific part of this paper refers to the big toe of "lowpower hand"-topologies.Review of topologies of CMOS logic series that ensure low-power within the specified range of operating frequencies is given, which implies their use in both strong and weak inversion regimes.
The analysis is based on simplified current-voltage models of MOS transistors and PSPICE software using parameters of 180 nm technology.

II. CMOS OPERATING IN THE WEAK INVERSION REGIME
In essence, there are three areas of MOS transistor static characteristics [7]. Figure 1 shows the logarithmic dependence of nMOS transistor drain current as a function of gate-source voltage (V gs ), at a constant drain-source voltage (V ds ) and source-substrate voltage (V sb ).In the literature, the smallest attention is paid to the medium (moderate) area which is mostly considered as a part of strong inversion threshold area [8,9].In digital circuits, it is assumed that V gs >V t , where V t is a MOS transistor's threshold voltage, transistor is operating in strong inversion regime, and for V gs <V t in the sub-threshold (weak inversion) regime.Therefore, from today's application point of view, it can be said that V t is a gate-source voltage on a border between the weak and the strong inversion regime.
It is a well-known fact that the I d (V ds , V gs ) characteristic in the strong inversion regime has two areas: non-saturated and saturated.In the non-saturated area, it holds that I d ~Vgs and I d ~Vds 2 , while in saturated area I d ~ V gs 2 and I d ≠ f(V ds ), that is I d ≈const as a function of V ds .MOS transistor characteristics in the weak inversion regime are defined as follows: ( ) is a drain current on a border between weak and strong inversion.The meaning of the parameters in (1) and (2) are the following: µ 0 is a mobility of major charge carriers (electrons and holes in nMOS to pMOS transistor), C ox = ε ox / t ox is gate capacitance (ε ox is a dielectric constant, t ox is a thickness of the gate oxide), W and L are the width and length of the channel, respectively, φ t =kT/q is a thermal potential (φ t =26 mV at T=300K), where n=1+C d /C ox ≈1.5 is a gradient factor.
For V ds >3φ t , drain current is almost independent of the voltage V ds (Figure 2), so that the area analogous to strong inversion regime, can be treated as saturated area.In this area it holds . For V ds <3φ t , at V gs =const., ds V d e I ~, transistor is in the non-saturated area.
Thanks to the analogy in the field of MOS transistor characteristics, there is an appropriate analogy of operation and CMOS logic circuit characteristics [8].Thus, for example, voltage and current static characteristics in the weak inversion regime (Figure 3) have the same shape as in the strong inversion regime.Even inverter threshold voltage V Tsub is obtained in the same way -equating of nMOS and pMOS drain currents in the saturated area of characteristics.

Id(Vgs, Vds) in weak inversion regime
It results with inverter threshold voltage V Tsub in the subthreshold regime [8]: and maximal current from the voltage source: is a supply voltage, V tn and V tp threshold voltages, and I on and I op currents on the border between weak and strong inversion of nMOS and pMOS transistors, respectively.For a symmetric inverter (I on =I op ), threshold voltage is, just like in strong inversion regime, V Tsub =V ddsub /2.
Minimal supply voltage, according to [7] is V ddmin =3φ t =78 mV.For V ddsub >3φ t , the I d (V gs , V ds ) characteristic has both saturated and non-saturated areas, which is necessary for satisfying the quality of digital circuit transfer characteristic V o (V i ).However, logic circuits can operate even at V dd <3φ t .Thus, for example, some authors [9] state constraints V dd >57 mV, while others [10] claim that V dd >48 mV.
As in strong inversion regime, threshold voltage V Tsub and maximal current I ddMsub in the sub-threshold regime both depend on nMOS and pMOS transistor geometry (Figure 3), except that I ddMsub ~(W n /W p ) -1/2 and V Tsub ~ln(W n /W p ), where W n and W p are the channel widths of nMOS and pMOS transistors, respectively.Considering the behavior analogy and CMOS inverter characteristics in the weak and strong inversion regime, there is an analogy even at synthesis of more complex circuits.In both regimes, more complex digital circuits consist of dual nMOS and pMOS transistor networks (Figure 4).Duality implies that a serial connection of nMOS transistors is corresponding to a parallel connection of pMOS transistors and vice versa.In both regimes, logic circuit transfer characteristic depends on the number of inputs and number of active inputs [8]. Figure 5a shows the transfer characteristics of NOR3 logic circuit with all inputs activated, and when the activated input is the one applied to the gate of a pMOS transistor whose source is connected on a power-supply line V dd .3 Fig. 5. PSPICE transfer characteristics of (a) NOR3 and (b) NAND2 circuits in the weak inversion regime, with all inputs activated, and when the activated input is the one applied on the gate of a serial transistor whose source connected on power supply line.
In NAND circuits, the highest threshold voltage is obtained when all inputs are active, and the lowest when the active input is only the one applied to the gate of nMOS transistors, whose source is connected to the ground (Figure 5b).Optimal transistor geometry of m-input NAND and NOR circuits is the same in both regimes and is defined as follows [12]:

III. CMOS CIRCUIT POWER CONSUMPTION
Electric power consumption consists of two components: static and dynamic Static consumption is a result of existing MOS transistor currents in static states and is defined as: where I S represents the static current in total.
There are four main sources of static current in CMOS circuits: • Tunneling current through the gate (I g ), • Sub-threshold drain current (I dsub ), • Inverse polarized p-n junction current (I DSS ), • Hot charge carrier injection gate current (I H ).
The first three components have dominant influence on CMOS circuit static consumption level.
Scaling of the dimensions of MOS transistors decreases oxide thickness below the gate (t ox ).Therefore, the electric field through gate oxide increases, which leads to the tunneling effect of charge carriers from gate to substrate or from substrate to gate.The gate current has four components: gate-channel (I gc ), gate-drain (I gd ), gate-source (I gs ) and gate-base (I gb ) (Fig. 6).The total gate current is:  Gate currents depend on supply voltage V dd and on the employed technology (Table I) [11].Thus, for example, when increasing the supply voltage level from V dd =0.2 V to V dd =1.2 V, the gate current increases from I g ≈1.2 nA to I g ≈1.7 µA.The increase ratio is approximately 1.4•10 3 times.When reducing the transistor dimensions, gate current increases as well.For nMOS transistor, according to Table I, that increase for 45 nm in regard to 65 nm CMOS technology, depending on V dd , is approximately 7 (at V dd =1.2 V) to 14 (at V dd =0.2 V) times.The nMOS transistor leakage current is greater than in pMOS, because the probability of holes tunneling is greater than the probability of electrons tunneling through the gate oxide.That increase, depending on supply voltage is 40 times [11].
The sub-threshold leakage current is a cutoff transistor (V gs =0) drain to source current (Figure 7) and it is given as:

www.etasr.com Dokic: A Review on Energy Efficient CMOS Digital Logic
where η is the DIBL (Drain-Induced Barrier Lowering) factor [9].
This current values depend on the supply voltage, the dimensions of elements (technology) and the temperature.In Table II, comparative values of gate current and sub-threshold drain current as a function of supply voltage V dd and temperature are given, for 45 nm technology.It is evident that the dependency of I g on V dd and in function of temperature dependency of I dsub is more expressed.On the other hand, at temperature of 25°C it holds V dd ≤ 0.6 V, I g <I dsub , while for V dd >0.6 V, I g >I dsub .Thus, for example, for V dd =1.2 V holds that I g ≈13I dsub .Inverse saturation current Idss of the p-n junction of a turned off transistor depends on the p-n junction surface and temperature.For 0.25 µm technology, it is between 10 and 100 pA/µm 2 at a 25°C temperature per area unit.In nanometer technologies, this current is less than I g and I dsub , and can be ignored.
Dynamic consumption consists of two components: switching consumption and transition (short-circuits) consumption.Switching consumption is the result of charging and discharging of a load capacitor and in both regimes is defined as: where C L is the effective output parasite capacitance, and f is the switching state frequency of the CMOS logic circuit.
Transition consumption occurs due to conduction of both transistors or transistor networks (nMOS or pMOS) during switching states (transition area) (Figure 3).In strong inversion regime, transition consumption is defined with [12] and is: where ( ) is the maximal voltage supply current in transition area, and t r and t f are the rise time and fall time input signals.
In sub-threshold regime, dissipation power of transition is defined with [8] : where I ddMsub is defined with (4), and f is an input signal frequency.
Usually, dynamic dissipation power is calculated (estimated) in regard to clock frequency.Namely, most number of logic circuits does not change their state during every cycle of clock signal.Therefore, expressions for dynamic consumption have to be multiplied with activity factor α≤1, regarding to clock frequency, so that: Product αf c , where f c is the clock frequency, is the activity of the circuit indicating the number of state changes.Mostly, activity factor is α<0.5.It is determined empirically that static CMOS digital circuits have α ≈ 0.1 [13].

IV. LOW POWER DESIGN TECHNIQUES
Optimal project implies a compromise between operating speed and low power, which all design levels take into account [2].In this section, we will speak about the optimal project considering the choice of transistor threshold voltage V t and system power supply voltage V dd .
In the previous paragraph, it was shown that both static and dynamic consumptions are decreased with the reduce of V dd .Dynamic switching consumption in both regimes is proportional to V dd 2 .Transition consumption in the strong inversion regime is P dp ~(V dd -V t ) 3 , and in sub-threshold regime  I and II), so that P S ~Vdd n , where n is usually in the range of 1<n<4.
Logic delay also depends on V dd and V t .Namely, in the strong inversion regime, capacitor charging/discharging current is I d ~(V dd -V t ) 2 in the saturated area, and I d ~ (V dd -V t )V o in the non-saturated area (Figure 8).In the sub-threshold regime that current is 8).Thus, reduction of V dd increases the logic delay in both regimes.In order to maintain the logic delay at lower V dd , threshold voltage V t should be reduced.Over a long period of time, CMOS digital circuit's performance increasing scenario was conducted in the process of reduction of element's dimensions, by lowering V dd and V t .However, reduction of V t below 200 mV leads to exponential increase of sub-threshold current as shown in ( 4).This may cause the static consumption to be higher than the dynamic.Consequently, it can be said that the reduction of threshold voltage is limited to approximately V tmin =200 mV.V. MULTI VDD /VT OPTIMIZATION TECHNIQUES A compromise between low power and sufficient speed can be achieved using transistors with different threshold voltages.This technique is known as the multi-threshold technique or MTCMOS [14,15].Critical signal path is designed using logic with lower threshold voltages.Transistors with higher V t are used where delay is not critical.The second approach with the MTCMOS technique is based on the so-called gated voltage supply (Figure 9).In static states, relatively in time of logic inactivity (Standby Mode), voltage supply is turned off using transistors with high threshold voltage.Thus, the small subthreshold current is secured, along with low static dissipation.Logic block transistors are designed with low V t so that the needed speed is preserved.
Using control "wake up" signal SL (Sleep), over a pMOS transistor with high V t , the connection between true V dd and virtual power supply V ddV is controlled.While M p is turned off, capacitor C B maintains the virtual power supply of the logic block.
Reduction of the leakage currents of inactive components can be achieved using nMOS transistors between the logic block and the ground, or with pMOS and nMOS transistors at the same time [15].The state of the pMOS transistors is then controlled with the SL signal, and of the nMOS with the SL signal.
The ratio between the consumption and the speed of data processing is optimized using several power supplies in the same design.Logic circuits over critical delay paths are supplied with higher V ddH , and circuits whose delay is not critical with lower voltage V ddL (Figure 10).The number of voltage levels can be greater, but it turns out that the largest effect is achieved using two power supplies [16].It should be noted that the transition from logic with V ddL to logic with V ddH power supply is achieved using logic voltage level converters.This as well limits the number of power supply levels.Often in the same digital system, techniques with several power supplies and several threshold voltages have been usedmulti V dd /V t techniques [16,17].Optimal operating point (V ddopt , V topt ) is determined on V dd -V t plane with constant power consumption lines (equi-power) and speed lines (equi-speed) (Fig. 11).These lines depend on technological process and project architecture.
The choice of the optimal (V ddopt ,V topt ) pair depends on technological process constraints.Let say that those constraints are: V dd =3.3V±10% and V t =0.55 V±0.1.The area of allowed values for these limitations is shown in Figure 11, with a larger rectangle.For all values of V dd and V t inside this rectangle, system fulfills all given specifications.In A corner, system will have the highest delay, and in B corner the highest energy consumption.Constant speed and constant consumption lines are normalized at points A and B by normalization factors k s and k p , respectively.Based on that, we determine the influence of position changes and the rectangle size in V dd -V t plane, onto consumption and system speed.For example, smaller rectangle on Figure 11 is defined with constraints V dd =2.1 V±5% and V t =0.18 V±0.05, and consumption is 60% (k p =0.4) lower for the same operating speed (k s =1).From all possible V dd -V t combinations that meet given time constraints, only one combination (V ddopt , V topt ) guarantees minimal consumption.Shuster et.al. [18] proposed an equation, based on the transistor alpha model, for the calculation of total system consumption with the optimal (V ddopt , V topt ) pair.Nevertheless, it should be stated that the continual change of V ddopt and V topt is unpractical.Designers are mostly allowed to choose between several discrete (V ddopt , V topt ) values.By applying the multi V dd technique, dynamic consumption can be reduced from 10%, up to 50%, whereas by applying the multi V t technique, static consumption can be reduced for 50%, even up to 80% [3].In [16], the optimal ratio between V dd and V t is given (Table III).

VI. CMOS LOW POWER TOPOLOGIES
Standard CMOS combinational logic demands a CMOS transistor pair per every input.However, various alternative topologies with the lower number of transistors have been developed.Besides, the increase of scale of function integration in VLSI integrated circuit, has led to a reduce of consumption or increase of speed at the same consumption level.
Among the first alternative CMOS digital logics is the transmission-gate logic.Unlike standard logic where the basic cell is the inverter, in transmission-gate logic, the basic cell is the transmission gate.While in standard logic circuits, output signals are separated from the inputs, here the input signal is transferred to the output via the transfer gate.Figure 12   In the synthesis of logical functions in transmission-gate logic, it must be taken into account that between the output and at least one input, a contour of small resistance exists.Otherwise, output would be in the state of high impedance with the undefined logic level.As a transmission gate, instead of a CMOS pair, only nMOS transistors can be used (Fig. 14).The number of transistors is halved and the static consumption and the parasite The problem with the nMOS pass-transistor logic is that the maximal voltage variation on one nMOS transistor is V dd -V tn and lower, for threshold voltage V tn comparing to the CMOS transmission gate.That limits the number of serial transistors.Therefore, nMOS transistors with very low (NTL-on Threshold Logic) or zero threshold voltage (ZTT-Zero Threshold Logic) have been used.The problem of mentioned logics lies in the low noise immunity.
Reduction of logic amplitude in nMOS transmission-gate logic is especially a problem when nMOS network ends with an inverter.That problem can be solved using a pMOS transistor M p as shown in Figure 16.When z = 0, M p is on and maintains the value of nMOS network output voltage at V dd .
Low threshold transistors are used in the so-called CPL (Complementary Pass-Transistor Logic).This logic consists of two nMOS transistor networks with common control and complementary transfer signals (Figure 15).PPL (Push-pull Pass-transistor Logic) [19] also have two transistor networks: one nMOS and the other pMOS (Figure 16).The control signals are common, and inputs are complementary.Output logic levels have been restored to V dd and 0 by transistors M p and M n , respectively.The Term "adiabatic" describes thermodynamic processes in which the amount of heat remains constant (there is no exchange of energy with the environment).Adiabatic logic in the ideal sense, designate digital circuits without loss (dissipation) of electrical energy.In practice, it denotes the logic with minimal consumption of electrical energy during the switching of states.Adiabatic switching state shifting is a charge/discharge mechanism which returns accumulated energy to the source inside the load capacitor using the dynamic power supply.Dynamic power supply or clocked power has a very important role in adiabatic logic, because beside power supply, it provides energy recovery.
Nowadays, there are many techniques of adiabatic logic [20][21][22][23][24][25].Energy recovery process will be explained on the example of ECRL (Efficient Charge Recovery Logic) inverter (Figure 17).Power supply PC is with trapezoidal pulses.In the initial state holds a=1, and the M n1 is conducting (Q=0).While PC rises from 0 to V dd , over conductive transistor M p2 the output Q follows the variation of PC.When PC reaches the V dd value, then it holds Q =1, and Q =0 and those conditions are valid logic states at inputs of next stage.During the fall of PC from V dd to zero, the right capacitor C L discharges over the conductive M p2 and PC, and therefore recovers accumulated energy to the PC supply.
More complex ECRL circuits have two complementary nMOS transistor networks with complementary excitations (Figure 18 Other adiabatic topologies should be mentioned as well: PAL (Pass-transistor Adiabatic Logic) [21], CPAL (Complementary PAL), PFAL (Positive Feedback Adiabatic Logic) [20] etc. Reduced energy consumption comparing to standard CMOS logic is around 50 to 90%.

VIII. CONCLUSION
To enable the design of energy-efficient digital systems, designers must take into account the electrical energy consumption through all design phases, from functional description to transistor level.The biggest energy saving (10 to 20 times) with the least time needed for consumption analysis is acquired on the system design level.In the sub-threshold regime, consumption is several orders of magnitude lower, but operating speed is lowered by nearly the same amount in comparison to the strong inversion regime.Rescaling of transistor dimensions increases gate current I g which is very dependent on power supply.Multi V t /V dd design techniques provide the reduction of consumption to a scale of about ten percent at the same operating speed.Digital systems with two power supplies and/or two threshold voltages are optimal as well.Using two threshold voltages, static consumption can be reduced up to 80%.Alternative topologies provide larger scale of function integration per single VLSI circuit, lower consumption level and higher-speed rate.The transfer logic has the widest application in VLSI digital circuit design whereas adiabatic logic ensures the greatest energy saving (up to 90%).

Fig. 1 .
Fig. 1. log Id characteristic as a function of Vgs at a constant Vds and Vsb

Fig. 4 .
Fig. 4. Topology of the circuit with logical function www.etasr.comDokic: A Review on Energy Efficient CMOS Digital Logic

−
. Static currents, depends on supply voltage as well (Tables

Fig. 8 .
Fig. 8. Discharge currents of capacitor CL in the strong and weak inversion regime

Fig. 11 .
Fig. 11.Vdd-Vt plain with constant power consumption and delay lines shows a 2/1 multiplexer (2/1 MUX) in transmission-gate logic.Since the complementary signals are needed for transmission gate control, inverters are integral part of the network as well.The 2/1 MUX in Figure 12 consists of only three CMOS transistor pairs, while standard logic needs seven pairs.

Fig. 12 .
Fig. 12. MUX 2/1 in transmission-gate logic Transmission gate logic can be additionally simplified by applying signals b and b to the inverter power line as in the example of XOR and XNOR circuit synthesis shown in Figure 13.The inverters with the (M n , M p ) transistor pair are powered by b and b signals.

For
), instead of M n1 and M n2 transistors.Complementary networks are obtained by complementing input signals and switching of logic operators as a function of f n nMOS network.

Fig. 18 .
Fig. 18.(a) Block scheme of complex ECRL circuit (b) with n f and n f

TABLE I .
NMOS TRANSISTOR GATE CURRENT AS A FUNCTION OF SUPPLY

TABLE II .
GATE AND SUB-THRESHOLD DRAIN CURRENT OF NMOS TRANSISTOR AS A FUNCTION OF VDD AND TEMPERATURE

TABLE III .
OPTIMAL RATIO OF VDD AND VT CONSIDERING CONSUMPTION

Table
IV shows full adder comparative characteristics using different logics, implemented in 0.8 µm technology at V dd =3.3 V.Although pMOS transistors are slower than nMOS, logic delay of PPL is approximately like CPL, but the consumption is significantly lower.

TABLE IV .
FULL ADDER COMPARATIVE CHARACTERISTICS