Performance Investigation of Different Topologies of 1-100 GHz on-chip Transformers using 130 nm SiGe BiCMOS

In this study, modeling and designing different topologies of on-chip transformers are presented using 130nm SiGe BiCMOS technology. Interleaved, stacked, and full symmetrical interleaved transformers are investigated. Octagon and square shapes are used for designing transformers with flipped and non-flipped feed lines. A comparison between performances of various configurations is presented using a fullwave simulator. The octagon stacked transformer with flipped feed lines showed a good performance at around 60GHz. The simulated results demonstrated a coupling factor K of 0.94, minimum insertion loss of 1.01518dB, and Q-factor of 9 with a minimum occupied area of 0.0019mm 2 . Keywords-on-chip transformer; 130nm SiGe BiCMOS technology; interleaved transformer; stacked transformer


INTRODUCTION
The growing demand for high quality and high data rate in a wireless telecommunication system increases the challenge for designing high performance electronics components. Particularly for a high frequency bands applications [1,2], the substrate losses in passive devices have become dominant due to the proximity and skin effect [3,4]. On-chip transformer (TF) is one of the passive components for designing system-onchip (SoC) applications. On-chip TF has been commonly used as a power splitter/combiner, and inter-stage impedance matching in many components design such as power amplifiers [5][6][7], low noise amplifiers [8,9], mixers [10], and voltage controlled oscillators [11][12][13]. The TF is better to be compact, low loss, with high quality factor, easy impedance matching, and with the ability of conversion from differential to single ended for power combining as well as conversion from single ended to differential for power splitting [14]. Many researches have been conducted in modeling and designing of the on-chip TF. The elements of the device can be extracted from the geometrical shape and technological data of the transformer [15]. However, this model is compatible up to 10GHz. Other broadband models for millimeter-wave TF working up to 100GHz, and 110GHz have been proposed in [16,17]. Moreover, an on-chip six ports TF model was reported in [18].
In this paper, a simple model based on lumped elements of TF is presented. In addition, direct parameters extraction based on EM S-parameters simulation is used for design and simulation of different topologies of on-chip transformer. IHP 130nm SiGe BiCMOS technology is considered in this study in the frequency range between 1-100GHz.

II. APPROACHES OF MODELING ON-CHIP TRANSFORMER
A transformer consists of two inductors for the primary and secondary windings. There are two approaches for extracting the parameters of these windings. The first method is using equivalent lumped components, while the second is direct parameter extraction from S-parameters using the EM Sonnet simulator. Figure 1 shows the equivalent circuit for the on-chip TF. The primary inductor has two ports, P1 and P2, the equivalent circuit model consists of six elements, three series elements represented by series capacitance Cp, inductance Lp, resistance Rp, as well as three substrate elements represented by oxide capacitance Cp-ox, substrate capacitance Cp_sub, and substrate resistance Rp_sub. The same elements have also been considered for the secondary inductor with two ports S1, and S2. Moreover, Cps represents the mutual capacitance between the two windings. The values for the six elements of the lumped equivalent circuit shown in Figure 2 can be calculated based on the dimensions of the inductor. The series inductor ‫ܮ‬ (nH) as a function of width w (µm), length l (µm), and thickness t (µm) can be calculated as [16]:  Figure 2 shows the relationship between inductance (pH) and length of inductor ( ߤ݉ ) with variable width ( ߤ݉ ) of inductor and constant thickness (3ߤ݉). It can be observed that, a smaller inductor width provides higher inductance. However, the width is constrained by the minimum width provided by the foundry. The rest of the parameters for the primary and secondary inductors can be calculated using the following formulas [19]: where, ߜ, ߪ, ߝ ௫ , ‫ݐ‬ ௫ are skin depth, conductivity, permittivity, and thickness of the oxide layer respectively, while ‫ܩ‬ ௦ and ‫ܥ‬ ௦ represent conductance and capacitance respectively for the silicon substrate ‫ܥ(‬ ௦ ≅ 10 ିଶ ‫݉ݑ/ܨ݂‬ ଶ , ‫ܩ‬ ௦ =10 ି ‫݉ݑ/ܵ‬ ଶ ).
Another approach for extracting parameters of the on-chip TF is using the 3D electromagnetic simulator (Sonnet) to generate the S-parameters. In that case, the following expressions are used for calculating primary inductance ‫ܮ‬ , secondary inductance ‫ܮ‬ ௦ , Q-factor for primary ܳ , Q-factor for secondary ܳ ௦ , and coupling coefficient K [20,21]: Moreover, the parameters of differential configuration for the on-chip TF can be extracted using [22]: where, ܼ ௗ , ‫ܮ‬ ௗ , and ܳ ௗ are differential impedance, differential inductance, and differential Q-factor respectively.

III. PERFORMANCE COMPARISON OF DIFFERENT TOPOLOGIES OF ON-CHIP TF DESIGN
Many topologies of the on-chip TF have been investigated. For stackup configuration top layers TM1 and TM2 were utilized to design primary and secondary windings. For the interleaved configuration TM2 layer was used for designing two windings, while TM1 layer was used for designing the secondary winding feed line. Figure Table I shows the dimensions of on-hp transformer for all topologies.  This work addresses the effect of windings position on the performance of on-chip TF. Lateral and vertical magnetic couplings are available according to the position of windings on the stackup layers. Lateral magnetic coupling takes place in interleaved configuration when utilizing only one thick layer TM2 for the primary and secondary windings. On the other hand, vertical magnetic coupling takes place between windings as in stacked topology when utilizing two thick layers, TM1 and TM2. In addition, feed lines' direction has a significant effect on the performance of on-chip TF. To compare the performance of the proposed topologies shown in Figure 3, design and simulation of on-chip TF by using the Sonnet EM simulation has been carried out. Figure 4 shows the comparison of primary and secondary inductance for all proposed topologies of on-chip TF. It can be observed that all topologies provide high resonant frequency, greater than 100GHz. The flipped feed lines of all topologies have greater inductance than the non-flipped ones. However, the flipped feed lines have slightly reduced coupling between windings. Therefore, for selection between the two options of feed lines position, the minimum space layout for specific circuit design should be considered. Amongst all topologies of the on-chip TF the symmetric square interleaved TF shape has the greatest inductance for primary and secondary windings. Both (SSTF) and (SOTF) have the same inductance for their primary and secondary windings because of their high symmetrical shapes. Figure 5 shows a comparison of Q-factor for all topologies. Both flipped and non-flipped feed line positions have been considered for simulation of the Q-factor of the primary and secondary windings. It can be seen that the transformers with flipped feed lines (represented by dash lines) have better values of Q-factor than the other transformers. The variation in primary and secondary values of Q-factor for the interleaved octagon and square shapes is due to the differences in their lengths of primary and secondary windings. However, the symmetric octagon and square transformers have almost the same values of Q-factors in their primary and secondary windings because they have full symmetrical shapes. Moreover, the octagon stacked transformers with flipped feed lines have better values of Q-factors than the one with nonflipped feed lines, which is because feed lines position in the same direction leads to imperfect coupling thus reducing quality factor. There are two approaches commonly used to find the figure-of-merit of TF. The first one is used when a TF is utilized in an application that requires high efficiency in power transmission. In this case the figure-of-merit can be calculated using maximum available gain G max . {23, 24]: (18) However, instead of using S-parameters, we can use Zparameters: The second method of determining the figure-of-merit of TF depends on the total loss of the device, using minimum insertion loss (ILm) expression [25]: On-chip TF has many sources of energy loss. Radiation loss takes place when dimension of the device is larger than the free space ߣ . Substrate coupling loss takes place according to capacitive coupling between substrate and conductor, therefore displacement current will leak into the substrate through lossy dielectric. In addition, ohmic losses (skin effect) as well as imperfect coupling between primary and secondary windings can be considered as a source of losses. Figure 6 shows the simulated minimum insertion loss (dB), and coupling factor K for all on-chip TF topologies. At high frequencies insertion loss increases, while K decreases according to the effect of imperfect coupling between TF windings. As seen in Figure 6(a) the octagon stacked transforms have the lowest insertion loss compared to the rest of TF topologies, while the symmetrical square transformer has the largest values of insertion loss due to their larger winding size. Because of the largest value of insertion loss for the symmetrical square transformer, this topology of TF has a worst value of coupling factor K as shown in Figure 6(b), while the octagon stacked TF provides the best values of K amongst all topologies.

IV. CONCLUSION
A comprehensive study of on-chip transformer using 130nm SiGe technology has been presented. Different topologies, shapes, and feed line positions of transformers have been investigated, using the top thick metals TM1 and TM2 of the stackup layer technology. Two methods of calculating elements of primary and secondary windings were explored, which are use of the geometry of windings and direct element extraction from the S-parameters. 3D electromagnetic simulation was carried out and the performance of transformers was compared in terms of inductance, quality factor, coupling  Figure 6: Comparison values of (a) Minimum insertion loss, and (b) Coupling factor K for different topologies of the on-chip TF